公开(公告)号：US08008771B2

公开(公告)日：2011-08-30

申请号：US12193561

申请日：2008-08-18

Applicant: Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

Inventor： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract translation: 一种半导体芯片封装，包括：半导体芯片，包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US07960778B2

公开(公告)日：2011-06-14

申请号：US12314163

申请日：2008-12-05

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0483 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/792

Abstract: The present invention relates to a flash memory cell string. The flash memory cell string includes a plurality of cell devices and switching devices connected to ends of the cell devices. Each of the cell devices includes a semiconductor substrate, and a transmissive insulating layer, a charge storage node, a control insulating layer and a control electrode sequentially formed on the semiconductor substrate. In the flash memory cell string, a buried insulating layer is provided on the semiconductor substrate between the cell device and an adjacent cell device, thus enabling an inversion layer, which performs the functions of source/drain, to be easily formed.According to the present invention, the reduction characteristics and performance of the cell devices of NAND flash memory are improved, and the inversion layer of a channel is induced through fringing electric fields from the control electrode and the charge storage node if necessary.

Abstract translation: 本发明涉及闪存单元串。 闪存单元串包括连接到单元设备的端部的多个单元设备和交换设备。 每个电池器件包括依次形成在半导体衬底上的半导体衬底和透射绝缘层，电荷存储节点，控制绝缘层和控制电极。 在闪速存储单元串中，在单元装置与相邻单元装置之间的半导体基板上设置掩埋绝缘层，能够容易地形成执行源/漏功能的反转层。 根据本发明，NAND闪存的单元装置的还原特性和性能得到改善，如果需要，通过来自控制电极和电荷存储节点的边缘电场来感应通道的反转层。

公开(公告)号：US20100219929A1

公开(公告)日：2010-09-02

申请号：US12738016

申请日：2008-10-14

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01H85/02

CPC classification number: H01H37/765

Abstract: Disclosed is a thermal fuse structured in such a manner that a resistance heating element which generates heat according to an electric current is mounted within a case charged with a solid fusible material so that the fusible material is liquefied by heat of the resistance heating element caused by the external temperature and also by the current applied to a circuit, accordingly disconnecting the circuit. Since the resistance heating element is integrally formed in the case, the thermal fuse is capable of functioning as both a thermal fuse and a current fuse, disconnecting the circuit by both the external heat and the overcurrent. Especially, when the resistance heating element comprises a positive thermal coefficient (PTC) element capable of temperature measurement, the current flowing through the circuit can be measured.

Abstract translation: 公开了一种热熔丝，其结构使得根据电流产生热量的电阻加热元件安装在装有固体可熔材料的壳体内，使得易熔材料由于电阻加热元件的热​​量而液化，由 外部温度以及施加到电路的电流，从而断开电路。 由于电阻加热元件在壳体中整体形成，所以热熔丝能够用作热熔丝和电流保险丝，同时通过外部热和过电流来断开电路。 特别地，当电阻加热元件包括能够进行温度测量的正热系数（PTC）元件时，可以测量流过电路的电流。

公开(公告)号：US07767512B2

公开(公告)日：2010-08-03

申请号：US12019449

申请日：2008-01-24

Applicant: Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

Inventor： Hyung-Suk Jung ,  Jong-Ho Lee ,  Sung-Kee Han ,  Yun-Ki Choi ,  Ha Jin Lim

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28026 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel.

Abstract translation: 在制造半导体器件的方法中，在包括第一导电类型的第一沟道和不同于第一导电类型的第二导电类型的第二沟道的衬底上形成栅极绝缘层。 在栅极绝缘层上形成包括第一金属的第一导电层，并且在形成在第二沟道上的第一导电层上形成包括不同于第一金属的第二金属的第二导电层。 通过湿式蚀刻工艺部分去除第二导电层，以在第二通道上形成第二导电层图案。

公开(公告)号：US20100163947A1

公开(公告)日：2010-07-01

申请号：US12632115

申请日：2009-12-07

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/40

Abstract: A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed.

Abstract translation: 一种PIP电容器及其方法。 制造PIP电容器的方法可以包括在硅衬底上形成场氧化物膜以限定器件隔离区和/或有源区。 制造PIP电容器的方法可以包括在场氧化物膜上形成具有掺杂杂质的下部多晶硅电极。 制造PIP电容器的方法可以包括执行氧化步骤以在活性区上和/或上方在多晶硅和/或第二氧化物膜上形成第一氧化膜。 制造PIP电容器的方法可以包括在第一氧化物膜的区域上和/或上方形成上部多晶硅电极，并且在基本上同时在第二氧化膜上形成和/或在第二氧化物膜上形成栅电极。 制造PIP电容器的方法可以包括形成多晶硅电阻器。 公开了一种PIP电容器。

公开(公告)号：US20100102372A1

公开(公告)日：2010-04-29

申请号：US12200929

申请日：2008-08-28

Applicant: Jong-Ho Lee ,  Ki-Heung Park

Inventor： Jong-Ho Lee ,  Ki-Heung Park

IPC: H01L27/108 ,  H01L21/84

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided are a high-performance one-transistor floating-body DRAM cell device and a manufacturing method thereof. The one-transistor floating-body DRAM cell device includes: a semiconductor substrate; a gate stack which is formed on the semiconductor substrate; a control electrode which is formed on the semiconductor substrate and surrounded by the gate stack; a floating body which is formed on the control electrode that is surrounded by the gate stack; source/drain which are formed at left and right sides of the floating body; an insulating layer which insulates the source/drain from the semiconductor substrate and the control electrode; a gate insulating layer which is formed on the floating body and the source/drain; and a gate electrode which is formed on the gate insulating layer. In the cell device having a double-gate structure, charges can be stored in a non-volatile manner by the control electrodes, so that it is possible to improve a degree of integration of devices, a uniformity of characteristic, and a sensing margin.

Abstract translation: 提供一种高性能单晶体体浮体DRAM单元装置及其制造方法。 单晶体体浮体DRAM单元装置包括：半导体基板; 形成在所述半导体基板上的栅极叠层; 控制电极，其形成在所述半导体基板上并被所述栅极堆叠包围; 浮动体，其形成在所述控制电极上，所述浮体被所述栅极叠层包围; 在浮体的左侧和右侧形成的源极/漏极; 绝缘层，其使源极/漏极与半导体衬底和控制电极绝缘; 形成在浮体和源极/漏极上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。 在具有双栅极结构的电池装置中，可以通过控制电极以非易失性的方式存储电荷，使得可以提高器件的集成度，特性的均匀性和感测裕度。

公开(公告)号：US20090156214A1

公开(公告)日：2009-06-18

申请号：US12316727

申请日：2008-12-16

Applicant: Joo-Hyun Lee ,  Jin-Ghoo Choi ,  Sang-Boh Yun ,  Jong-Ho Lee ,  Yong-Soo Cho ,  Jae-Kwon Kim ,  Yeong-Jun Kim ,  Kyung-Soo Woo ,  Hyun-Il Yoo

Inventor： Joo-Hyun Lee ,  Jin-Ghoo Choi ,  Sang-Boh Yun ,  Jong-Ho Lee ,  Yong-Soo Cho ,  Jae-Kwon Kim ,  Yeong-Jun Kim ,  Kyung-Soo Woo ,  Hyun-Il Yoo

IPC: H04W36/00

CPC classification number: H04W36/30 ,  H04B7/2606 ,  H04W16/26

Abstract: Provided is a handover method of a wireless communication system using a hierarchical cellular scheme. In the method, signal quality of a serving node is measured, so that whether to start scanning for a handover is determined. When the scanning for the handover starts, signal qualities of a serving cell including the serving node and one or more neighbor cells are measured through a first preamble including a first identifier for distinguishing a cell. An intra-cell handover or an inter-cell handover is selected using the signal qualities of the serving cell and the neighbor cells. Therefore, a terminal can easily distinguish between the inter-cell handover and the intra-cell handover, and an overhead during a handover can be reduced because an intra-cell handover procedure is simplified.

Abstract translation: 提供了使用分层蜂窝方案的无线通信系统的切换方法。 在该方法中，测量服务节点的信号质量，从而确定是否开始扫描切换。 当切换的扫描开始时，包括服务节点和一个或多个相邻小区的服务小区的信号质量通过包括用于区分小区的第一标识符的第一前同步码进行测量。 使用服务小区和相邻小区的信号质量来选择小区内切换或小区间切换。 因此，终端可以容易地区分小区间切换和小区内切换，并且可以减少切换期间的开销，因为小区内切换过程被简化。

公开(公告)号：US20090086840A1

公开(公告)日：2009-04-02

申请号：US12284922

申请日：2008-09-26

Applicant: Sung-Yoon Jung ,  Sang-Boh Yun ,  Sung-Soo Hwang ,  Jong-Ho Lee

Inventor： Sung-Yoon Jung ,  Sang-Boh Yun ,  Sung-Soo Hwang ,  Jong-Ho Lee

IPC: H04L5/12 ,  H04L27/28

CPC classification number: H04L25/03343 ,  H04L5/0053 ,  H04L2025/03414 ,  H04L2025/03802

Abstract: Disclosed is a system and method for transmitting feedback information in a communication system. A receiver calculates a minimum distance of each two symbol vectors among all symbol vectors which can be received through a kth subcarrier among a plurality of subcarriers, in which a channel state of the kth subcarrier and a jth precoder among precoders included in a codebook set are applied; calculates sums of minimum distances by adding minimum distances calculated for the plurality of subcarriers according to each precoder; determines a precoder corresponding to a value greatest among the sums of minimum distances calculated according to the precoders, as a precoder representing the plurality of subcarriers; and feeds the feedback information including a precoder index of the determined precoder back to a transmitter.

Abstract translation: 公开了一种用于在通信系统中发送反馈信息的系统和方法。 接收机计算在多个子载波中可以通过第k个子载波接收的所有符号向量中的每两个符号向量的最小距离，其中包括在码本集中的预编码器中的第k个副载波和第j个预编码器的信道状态是 应用; 通过根据每个预编码器添加针对多个子载波计算的最小距离来计算最小距离的和; 确定对应于根据预编码器计算的最小距离之和中最大值的预编码器作为表示多个子载波的预编码器; 并将包括所确定的预编码器的预编码器索引的反馈信息反馈给发射机。

公开(公告)号：US20080298491A1

公开(公告)日：2008-12-04

申请号：US12154954

申请日：2008-05-28

Applicant: Sung-Yoon Jung ,  Sang-Boh Yun ,  Young-Hoon Kwon ,  Sung-Soo Hwang ,  Jong-Ho Lee ,  Hyun-Cheol Park ,  Hyoun-Kuk Kim ,  Ki-Hwan Jeon

Inventor： Sung-Yoon Jung ,  Sang-Boh Yun ,  Young-Hoon Kwon ,  Sung-Soo Hwang ,  Jong-Ho Lee ,  Hyun-Cheol Park ,  Hyoun-Kuk Kim ,  Ki-Hwan Jeon

IPC: H04L27/28

CPC classification number: H04L25/0206

Abstract: An apparatus and a method are provided for detecting N number of TX signals in a MIMO wireless communication system. The apparatus includes an RF processor, a channel estimator, and a signal detector. The RF processor converts signals, received through multiple antennas, into baseband signals. The channel estimator estimates channel information of the respective antennas by using the received signals. The signal detector arranges the baseband signals of the respective antennas on the basis of the channel information, calculates a threshold value of each stage, and selects symbols with a cumulative metric smaller than or equal to the threshold value as candidates at each stage, to detect a TX signal vector with N number of symbols.

Abstract translation: 提供了一种用于在MIMO无线通信系统中检测N个TX信号的装置和方法。 该装置包括RF处理器，信道估计器和信号检测器。 RF处理器将通过多个天线接收的信号转换为基带信号。 信道估计器通过使用所接收的信号来估计各个天线的信道信息。 信号检测器基于信道信息布置各个天线的基带信号，计算每一级的阈值，并且选择具有小于或等于阈值的累积度量的符号作为每个级的候选，以检测 具有N个符号的TX信号向量。

公开(公告)号：US07459359B2

公开(公告)日：2008-12-02

申请号：US11556804

申请日：2006-11-06

Applicant: Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

Inventor： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

Abstract translation: 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。