公开(公告)号：US20070066018A1

公开(公告)日：2007-03-22

申请号：US11556804

申请日：2006-11-06

申请人： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

发明人： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

摘要翻译： 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。

公开(公告)号：US07459359B2

公开(公告)日：2008-12-02

申请号：US11556804

申请日：2006-11-06

申请人： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

发明人： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

摘要翻译： 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。

公开(公告)号：US20050145932A1

公开(公告)日：2005-07-07

申请号：US10780067

申请日：2004-02-17

申请人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

发明人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786 ,  H01L29/10

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

摘要翻译： 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝衬底延伸超过源/漏极的绝缘层 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

公开(公告)号：US07148541B2

公开(公告)日：2006-12-12

申请号：US10780067

申请日：2004-02-17

申请人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

发明人： Tai-su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

IPC分类号： H01L27/01

CPC分类号： H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

摘要： A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

摘要翻译： 场效应晶体管可以包括从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，以及在垂直沟道的侧壁上朝向衬底延伸到源极/漏极 区域交界处 晶体管还可以包括在离开衬底的侧壁上延伸超过绝缘层的氮化物层，在侧壁上延伸的第二绝缘层，其通过氮化物层与沟道分离，以及栅电极 侧壁朝向衬底以超出源/漏区结。 还公开了相关方法。

公开(公告)号：US20100072545A1

公开(公告)日：2010-03-25

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹陷。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US08691649B2

公开(公告)日：2014-04-08

申请号：US13151494

申请日：2011-06-02

申请人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

摘要翻译： 在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。 可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。 可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。 可以在栅极氧化物层上形成栅电极以填充凹部。 源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。 因此，氧化物层可以具有均匀的厚度分布和致密结构。

公开(公告)号：US20090325356A1

公开(公告)日：2009-12-31

申请号：US12432500

申请日：2009-04-29

申请人： Dong-Woon SHIN ,  Si-Young Choi ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Dong-Woon SHIN ,  Si-Young Choi ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/426

CPC分类号： H01L21/02274 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/2236 ,  H01L21/2652 ,  H01L21/26546 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6659

摘要： Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity.

摘要翻译： 提供形成低温沉积层的方法和使用其制造半导体器件的方法。 制造半导体器件的方法包括：在掩模层上形成掩模层，在其上形成栅极图案的衬底上露出栅极图案，在掩模层上形成牺牲层，并在未被掩模层覆盖的衬底上使用等离子体离子浸没 注入和沉积（PIIID），并且用杂质掺杂与栅极图案的两个侧壁相邻的衬底。

公开(公告)号：US20090068823A1

公开(公告)日：2009-03-12

申请号：US12145914

申请日：2008-06-25

申请人： Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

发明人： Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

IPC分类号： H01L21/02 ,  H01J37/08

CPC分类号： H01L21/2236 ,  H01J37/32412 ,  H01J37/32449

摘要： In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.

摘要翻译： 在等离子体离子掺杂操作中，将晶片定位在反应室内的基座上，并且将离子掺杂源气体在晶片的主表面上方的反应室上部进行等离子化，同时将控制气体供应到反应室中 反应室的下部与晶片的主表面相对，从而将离子掺杂到晶片的主表面。 离子掺杂源气体可以包括至少一种卤化物气体，并且控制气体可以包括至少一种沉积气体，例如硅烷气体。 在另外的实施方案中，可以向反应室供应诸如惰性气体的稀释气体，同时供应离子掺杂源气体和控制气体。 描述了相关的等离子体离子掺杂装置。

公开(公告)号：US20080048262A1

公开(公告)日：2008-02-28

申请号：US11892320

申请日：2007-08-22

申请人： Deok-Hyung Lee ,  Sun-Ghil Lee ,  Gyeong-Ho Buh ,  Jong-Ryeol Yoo ,  Si-Young Choi ,  Tai-Su Park

发明人： Deok-Hyung Lee ,  Sun-Ghil Lee ,  Gyeong-Ho Buh ,  Jong-Ryeol Yoo ,  Si-Young Choi ,  Tai-Su Park

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/7851 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L2029/7858

摘要： Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.

摘要翻译： 提供具有凹陷源极/漏极区域的鳍式场效应晶体管（FinFET）及其形成方法。 一个示例性实施例可以提供一种半导体器件，其包括设置在基板上并沿第一方向延伸的鳍，所述鳍包括台阶部分，以及沿与第一方向交叉的第二方向延伸的栅电极，并且设置在顶表面上 翅片的台阶部分的侧表面。

公开(公告)号：US09190495B2

公开(公告)日：2015-11-17

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹部。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。