公开(公告)号：US06577553B2

公开(公告)日：2003-06-10

申请号：US10123167

申请日：2002-04-17

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato ,  Shinichi Kobayashi

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2207/2227

摘要： Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

公开(公告)号：US06331958B1

公开(公告)日：2001-12-18

申请号：US09725856

申请日：2000-11-30

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C700

摘要： A semiconductor memory device according to the present invention includes a memory core portion, a test mode control circuit for transmitting data output from the memory core portion to an internal node, and a data input/output control circuit for inputting/outputting in series a plurality of pieces of parallel data input/output to each internal node to a data node. The test mode control circuit transmits read data from the memory core portion as it is to the internal node in a normal reading operation, and compresses data output from the memory core portion on the basis of a prescribed unit and transmits the data to the internal node in a test mode. Therefore, the test data compressed for each prescribed unit can be input/output by using a smaller number of data nodes in the test mode than in the normal operation mode.

公开(公告)号：US06205067B1

公开(公告)日：2001-03-20

申请号：US09480498

申请日：2000-01-11

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C2900

CPC分类号： G11C29/06 ,  G11C5/00 ,  G11C11/401 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/34 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/2602

摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

摘要翻译： 压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。 对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线 字线到选定状态。 可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。 在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。

公开(公告)号：US5966340A

公开(公告)日：1999-10-12

申请号：US960286

申请日：1997-10-29

申请人： Takeshi Fujino ,  Masaki Tsukude

发明人： Takeshi Fujino ,  Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C8/14 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/18 ,  G11C8/14

摘要： Conductive lines for electrostatic shielding including at least one signal line are arranged between a global data I/O bus line and a ground line transmitting a ground voltage to a nonselected word line through a sub-decoder. Capacitive coupling between bus lines included in the global data I/O bus and the ground line is suppressed, and floating up of a ground voltage on the nonselected word line is prevented.

摘要翻译： 包括至少一条信号线的用于静电屏蔽的导电线被布置在全局数据I / O总线与通过子解码器将接地电压发送到非选择字线的接地线之间。 包含在全局数据I / O总线和地线之间的总线之间的电容耦合被抑制，并且防止非选定字线上的接地电压浮起。

公开(公告)号：US5910927A

公开(公告)日：1999-06-08

申请号：US931525

申请日：1997-09-16

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/065 ,  G11C8/10 ,  G11C8/14

摘要： A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).

摘要翻译： 提供具有较小电路面积但有效使用的存储器件。 沿着行方向延伸的多条主字线（MWL）通过相应的存储体锁存器（BL）连接到跨越银行（BANK0，BANK1）延伸的单个全局字线（GWL）。 使能信号（BLE）和全局字线（GWL）的选择性激活选择一个存储体锁存器（BL）来选择性地激活相关联的主字线（MWL）。 在使能信号（BLE）失效之后，该状态由选择的存储体锁存器（BL）保持。 然后，激活另一个使能信号（BLE）以选择性地激活另一主字线（MWL）。 连接到主字线（MWL）的子解码器（SD）彼此独立地选择，以独立地激活每个银行（BANK）的字线（WL）。

公开(公告)号：US5894448A

公开(公告)日：1999-04-13

申请号：US944642

申请日：1997-10-06

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/025

摘要： Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.

摘要翻译： 设置在通过划分半导体芯片形成的四个区域中的存储器垫每个被进一步沿着芯片的较长边方向分成多个存储器阵列，行相关电路沿着芯片的较短边方向设置在存储器阵列之间，并且 沿芯片的长边方向设置列解码器。 来自芯片中心的主控制电路的内部控制信号相对于芯片的短边方向在中央区域传输，缓冲电路被提供给内部控制信号传输总线，内部信号为 通过缓冲电路传输到行相关电路和列解码器。 要驱动的信号线的长度被缩短，因此可以高速传输信号，从而实现高速访问。 因此，即使芯片尺寸增加，也可以降低信号传播延迟。

公开(公告)号：US07693004B2

公开(公告)日：2010-04-06

申请号：US12014071

申请日：2008-01-14

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.

摘要翻译： 本发明公开了一种具有产生驱动电源电压的电压供给电路的半导体存储器件。 电压供给电路设置有用于将驱动器电源电压预充电到存储单元的电源电压电平的第一电压供给电路和用于提供低于存储器的电源电压电平的电压的第二电压供应电路 电池作为驱动器电源电压。

公开(公告)号：US07447098B2

公开(公告)日：2008-11-04

申请号：US11976354

申请日：2007-10-24

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

摘要翻译： 在具有完全隐藏刷新功能的DRAM中，当在活动模式下执行数据刷新时，用于选择路径的信号被设置为“H”电平，然后在每个周期重置为“L”电平 指定相应的上位地址。 当在待机模式下进行数据更新时，选择路径的信号保持在“H”电平，并且在指定相应的上位地址时不会重置为“L”电平。 这可以减少待机电流。

公开(公告)号：US07301843B2

公开(公告)日：2007-11-27

申请号：US11375079

申请日：2006-03-15

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

摘要翻译： 在具有完全隐藏刷新功能的DRAM中，当在活动模式下执行数据刷新时，用于选择路径的信号被设置为“H”电平，然后在每个周期重置为“L”电平 指定相应的上位地址。 当在待机模式下进行数据更新时，选择路径的信号保持在“H”电平，并且在指定相应的上位地址时不会重置为“L”电平。 这可以减少待机电流。

公开(公告)号：US20060050587A1

公开(公告)日：2006-03-09

申请号：US11215994

申请日：2005-09-01

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/40603 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615

摘要： A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.