公开(公告)号：US20060104113A1

公开(公告)日：2006-05-18

申请号：US11271300

申请日：2005-11-10

申请人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

发明人： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

摘要翻译： 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US07033899B2

公开(公告)日：2006-04-25

申请号：US11018242

申请日：2004-12-22

申请人： Cha-Hsin Lin ,  Zing-Way Pei ,  Shing-Chii Lu ,  Wen-Yi Hsieh

发明人： Cha-Hsin Lin ,  Zing-Way Pei ,  Shing-Chii Lu ,  Wen-Yi Hsieh

IPC分类号： H01L21/8228

CPC分类号： H01L21/823807 ,  H01L21/31155 ,  H01L29/7843

摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

公开(公告)号：US06277736B1

公开(公告)日：2001-08-21

申请号：US09206884

申请日：1998-12-08

申请人： L. Y. Chen ,  Heinz Shih ,  Wen-Yi Hsieh ,  Tsu-An Lin

发明人： L. Y. Chen ,  Heinz Shih ,  Wen-Yi Hsieh ,  Tsu-An Lin

IPC分类号： H01L2144

CPC分类号： H01L21/32137 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32136

摘要： A method for forming a gate. A gate oxide layer, a polysilicon layer and a barrier layer are subsequently formed on a substrate, on which an isolation structure is formed. A conductive layer is formed on the barrier layer by sputtering deposition using titanium silicide with a low silicon content as a target. A rapid thermal process (RTP) is performed to remove the polymer nodule formed by sputtering deposition. An anti-reflection layer is formed on the conductive layer. The anti-reflection layer, the conductive layer and the barrier layer are patterned by the etchant composed of chlorine/nitrogen/hexafluoroethane until the polysilicon layer is exposed. Using the anti-reflection layer, the conductive layer and the barrier layer as a mask, the exposed polysilicon layer and the gate oxide layer underlying the exposed polysilicon layer are removed by the etchant composed of chlorine/hydrogen bromide/helium/oxygen until the substrate is exposed and a gate is formed.

摘要翻译： 一种形成栅极的方法。 随后在其上形成有隔离结构的基板上形成栅极氧化物层，多晶硅层和势垒层。 通过使用具有低硅含量的硅化钛作为靶的溅射沉积在阻挡层上形成导电层。 进行快速热处理（RTP）以除去由溅射沉积形成的聚合物结节。 在导电层上形成防反射层。 通过由氯/氮/六氟乙烷组成的蚀刻剂将抗反射层，导电层和阻挡层图案化，直到多晶硅层露出。 使用防反射层，导电层和阻挡层作为掩模，暴露的多晶硅层和暴露的多晶硅层下面的栅极氧化物层被由氯/溴化氢/氦/氧组成的蚀刻剂除去直到基板 被暴露并形成门。

公开(公告)号：US06174765B1

公开(公告)日：2001-01-16

申请号：US09010005

申请日：1998-01-21

申请人： Wen-Yi Hsieh ,  Kuo-Tai Huang

发明人： Wen-Yi Hsieh ,  Kuo-Tai Huang

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L21/31691 ,  H01L27/1085

摘要： A method of reducing the leakage current of a dielectric layer of a capacitor. A substrate having a dielectric layer formed thereon is disposed into a furnace. A first annealing step is performed for nucleation. A second annealing step is performed to control the number of the nuclei. A third annealing step is performed for grain growth.

摘要翻译： 一种降低电容器的电介质层的漏电流的方法。 将其上形成有电介质层的基板设置在炉中。 进行成核的第一退火步骤。 执行第二退火步骤以控制核的数量。 进行晶粒生长的第三退火步骤。

公开(公告)号：US6083789A

公开(公告)日：2000-07-04

申请号：US60323

申请日：1998-04-14

申请人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A method for forming a DRAM capacitor whose titanium nitride electrode is fabricated in a sequence of steps that results in a good step-coverage. Moreover, contamination of the titanium nitride layer and cross-diffusion between the titanium nitride layer and the dielectric film layer is reduced to a minimum. The method of forming the titanium nitride layer includes the steps of depositing a first titanium nitride layer over a dielectric film layer using a conventional physical vapor deposition process. Then, a second titanium nitride layer is deposited over the first titanium nitride layer using a collimated physical vapor deposition process.

摘要翻译： 一种形成DRAM电容器的方法，其中氮化钛电极以一系列步骤制造，这导致良好的阶梯覆盖。 此外，氮化钛层的污染和氮化钛层与电介质膜层之间的交叉扩散减少到最小。 形成氮化钛层的方法包括以下步骤：使用常规的物理气相沉积工艺在电介质膜层上沉积第一氮化钛层。 然后，使用准直的物理气相沉积工艺在第一氮化钛层上沉积第二氮化钛层。

公开(公告)号：US6057189A

公开(公告)日：2000-05-02

申请号：US24183

申请日：1998-02-17

申请人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Wen-Kuan Yeh ,  Tri-Rung Yew

发明人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Wen-Kuan Yeh ,  Tri-Rung Yew

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/822 ,  H01L21/8242

CPC分类号： H01L28/40 ,  Y10S438/964

摘要： A method of fabricating a capacitor, comprising the steps of: providing a conductive layer over a semiconductor substrate having a transistor formed thereon to connect a source/drain region of the transistor; forming a hemispherical grained silicon layer over the conductive layer; using an implantation method to implant ions into the hemispherical grained silicon layer; performing a thermal treatment process to convert the ions into a barrier layer over the hemispherical grained silicon layer; performing a wet etching process to clean a surface of the barrier layer; forming a dielectric layer over the barrier layer and forming a top electrode over the dielectric layer.

摘要翻译： 一种制造电容器的方法，包括以下步骤：在其上形成有晶体管的半导体衬底上提供导电层以连接晶体管的源极/漏极区域; 在所述导电层上形成半球形晶粒硅层; 使用植入方法将离子注入到半球形晶粒硅层中; 执行热处理工艺以将离子转换成半球形晶粒硅层上的阻挡层; 执行湿蚀刻工艺以清洁阻挡层的表面; 在阻挡层上形成电介质层，并在电介质层上形成顶部电极。

公开(公告)号：US5994183A

公开(公告)日：1999-11-30

申请号：US996696

申请日：1997-12-23

申请人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

发明人： Kuo-Tai Huang ,  Wen-Yi Hsieh ,  Tri-Rung Yew

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/60 ,  H01L21/28518 ,  H01L27/10852

摘要： A method for forming a high capacitance charge storage structure that can be applied to a substrate wafer having MOS transistor already formed thereon. The method is to form an insulating layer above the substrate wafer. Next, a contact window exposing a source/drain region is formed in the insulating layer. Then, a tungsten suicide layer, which functions as a lower electrode for the charge storage structure, is formed over the substrate. Thereafter, a tungsten nitride layer is formed over the tungsten silicide layer, and then a dielectric layer is formed over the tungsten nitride layer. The dielectric layer is preferably a tantalum oxide layer. Finally, a titanium nitride layer, which functions as an upper electrode for the charge storage structure, is formed over the tantalum oxide layer.

摘要翻译： 一种用于形成可以应用于已经形成有MOS晶体管的衬底晶片的高电容电荷存储结构的方法。 该方法是在衬底晶片之上形成绝缘层。 接下来，在绝缘层中形成暴露源极/漏极区域的接触窗口。 然后，在基板上形成用作电荷存储结构的下电极的硅化钨层。 此后，在硅化钨层之上形成氮化钨层，然后在氮化钨层上形成电介质层。 电介质层优选为氧化钽层。 最后，在钽氧化物层上形成用作电荷存储结构的上电极的氮化钛层。