公开(公告)号：US06933191B2

公开(公告)日：2005-08-23

申请号：US10605260

申请日：2003-09-18

申请人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

发明人： Glenn A. Biery ,  Zheng G. Chen ,  Timothy J. Dalton ,  Naftali E. Lustig

IPC分类号： H01L21/02 ,  H01L21/027 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L28/20 ,  H01L21/0274 ,  H01L28/40

摘要： MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.

摘要翻译： MIM电容器和薄膜电阻器与现有技术的方法相比制造的光刻步骤至少少一个。 通过使用通过双掩模工艺制造的半透明金属电极实现工艺步骤减少，其提供直接对准，并且不需要在附加层中对准沟槽。

公开(公告)号：US06831363B2

公开(公告)日：2004-12-14

申请号：US10319032

申请日：2002-12-12

申请人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

摘要翻译： 用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。 形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。 通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

公开(公告)号：US06815813B1

公开(公告)日：2004-11-09

申请号：US10604211

申请日：2003-07-01

申请人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Kevin S. Petrarca ,  Michelle L. Steen ,  Cornelia K. Tsang ,  Richard P. Volant

IPC分类号： H01L2334

CPC分类号： H01L23/58 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.

摘要翻译： 提供了一种从制热电子设备散热的系统和方法。 该系统包括用于制造集成电路的基板，该基板具有第一面和第二面。 第二面基本上平行于第一面设置，其中设置有电子装置。 在电子设备周围的第一面设有金属化的裂纹停止件。 多个第一金属导管从其第二面延伸穿过基板到裂缝停止部，其中每个第一金属导管与裂纹停止件热接触以提供从电子装置到第二面的热耗散。

公开(公告)号：US06798029B2

公开(公告)日：2004-09-28

申请号：US10434999

申请日：2003-05-09

申请人： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

发明人： Richard P. Volant ,  John C. Bisson ,  Donna R. Cote ,  Timothy J. Dalton ,  Robert A. Groves ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Seshadri Subbanna

IPC分类号： H01L2982

CPC分类号： H01H59/0009 ,  H01H2059/0018 ,  H01H2059/0072

摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

摘要翻译： 描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。 该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。 该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。 铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。 在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。 气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。 代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。 下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。 通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。 然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。 然后用牺牲脱模材料填充空腔。 然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

公开(公告)号：US08487401B2

公开(公告)日：2013-07-16

申请号：US13359634

申请日：2012-01-27

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L23/522

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20120183743A1

公开(公告)日：2012-07-19

申请号：US13432036

申请日：2012-03-28

申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

IPC分类号： B32B3/30

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

公开(公告)号：US20120183742A1

公开(公告)日：2012-07-19

申请号：US13430179

申请日：2012-03-26

申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl J. Radens

发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl J. Radens

IPC分类号： B32B3/10 ,  B32B3/30

CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

公开(公告)号：US20120183736A1

公开(公告)日：2012-07-19

申请号：US13430177

申请日：2012-03-26

申请人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

发明人： Charles T. Black ,  Timothy J. Dalton ,  Bruce B. Doris ,  Carl Radens

IPC分类号： B32B3/10 ,  B32B3/30

CPC分类号： H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

公开(公告)号：US08198103B2

公开(公告)日：2012-06-12

申请号：US12170634

申请日：2008-07-10

申请人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Timothy J. Dalton ,  Wesley C. Natzle ,  Paul W. Pastel ,  Richard S. Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/32137 ,  Y10S438/909

摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.

摘要翻译： 一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。 使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。 压载气体可以类似于或等同于在处理室内产生的气态副产物。 压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。 这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。 当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。 钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

公开(公告)号：US08119491B2

公开(公告)日：2012-02-21

申请号：US12106374

申请日：2008-04-21

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。