公开(公告)号：US20220246215A1

公开(公告)日：2022-08-04

申请号：US17726059

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/04

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US11335404B2

公开(公告)日：2022-05-17

申请号：US17080553

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US11309052B2

公开(公告)日：2022-04-19

申请号：US17001723

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/42 ,  G11C29/44 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20220068426A1

公开(公告)日：2022-03-03

申请号：US17001723

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/12 ,  G06F11/07 ,  G06F11/30

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20220066642A1

公开(公告)日：2022-03-03

申请号：US17006978

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A method includes performing a copyback operation comprising transferring, using an internal processing device, user data and header data corresponding to the user data from a first block of memory in a memory device to a register in the memory device, decoupling the user data from the header data, performing an error correction code (ECC) operation on updated header data using an external processing device, transferring, via the external processing device, the updated header data to the register, and transferring the user data and the updated header data from the register to a second block of memory in the memory device.

公开(公告)号：US20210265499A1

公开(公告)日：2021-08-26

申请号：US17316943

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L21/425 ,  H01L29/10 ,  H01L27/11582 ,  H01L29/786 ,  H01L27/1157

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US20210202751A1

公开(公告)日：2021-07-01

申请号：US16781733

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Marc Aoulaiche

IPC: H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11556

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure coupled adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

公开(公告)号：US10937482B2

公开(公告)日：2021-03-02

申请号：US16432250

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Ankit Sharma ,  Haitao Liu ,  Albert Fayrushin ,  Akira Goda ,  Kamal M. Karda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/105

Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.

公开(公告)号：US20210057434A1

公开(公告)日：2021-02-25

申请号：US16547885

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20210057424A1

公开(公告)日：2021-02-25

申请号：US16549519

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.