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    Wafer-scale memory techniques
    92.
    发明授权
    Wafer-scale memory techniques 有权

    公开(公告)号：US11621257B2

    公开(公告)日：2023-04-04

    申请号：US17162796

    申请日：2021-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Bambi L. DeLaRosa ,  Eiichi Nakano

    IPC: G11C5/06 ,  G06F3/06 ,  H01L25/00 ,  H01L25/18 ,  H01L21/00 ,  G11C29/00 ,  H01L27/108

    Abstract: Techniques for wafer-scale memory device and systems are provided. In an example, a wafer-scale memory device can include a large single substrate, multiple memory circuit areas including dynamic random-access memory (DRAM), the multiple memory circuit areas integrated with the substrate and configured to form an array on the substrate, and multiple streets separating the memory circuit areas. The streets can accommodate attaching the substrate to a wafer-scale processor. In certain examples, the large, single substrate can have a major surface area of more than 20,000 square millimeters (mm2).

    Memory module multiple port buffer techniques
    93.
    发明授权
    Memory module multiple port buffer techniques 有权

    公开(公告)号：US11538508B2

    公开(公告)日：2022-12-27

    申请号：US17137975

    申请日：2020-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

    IPC: G11C7/10 ,  G11C7/22

    Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

    STACKED MEMORY ROUTING TECHNIQUES
    95.
    发明申请
    STACKED MEMORY ROUTING TECHNIQUES 有权

    公开(公告)号：US20220208734A1

    公开(公告)日：2022-06-30

    申请号：US17582612

    申请日：2022-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L25/18 ,  H01L25/00 ,  H01L23/48 ,  G11C5/04 ,  G11C5/06

    Abstract: Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

    MEMORY EXPANSION CARD
    96.
    发明申请
    MEMORY EXPANSION CARD 有权

    公开(公告)号：US20220179463A1

    公开(公告)日：2022-06-09

    申请号：US17541524

    申请日：2021-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth

    IPC: G06F1/18 ,  G06F1/20 ,  G06F1/3225 ,  G06F13/16 ,  G06F13/40

    Abstract: The present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. The memory expansion card can have on-die error correction code (ECC) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. A memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. The controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.

    Protected regions management of memory
    97.
    发明授权
    Protected regions management of memory 有权

    公开(公告)号：US11126453B2

    公开(公告)日：2021-09-21

    申请号：US16295708

    申请日：2019-03-07

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Naveh Malihi

    IPC: G06F9/455 ,  H04L9/14 ,  G06F12/14 ,  G06F21/62

    Abstract: Apparatuses and methods related to managing regions of memory are described. Managing regions can include verifying whether an access command is authorized to access a particular region of a memory array, which may have some regions that have rules or restrictions governing access (e.g., so-called “protected regions”). The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the region, then a row of the memory array corresponding to the access command may not be activated.

    Apparatus and method of power transmission sensing for stacked devices
    99.
    发明授权
    Apparatus and method of power transmission sensing for stacked devices 有权

    公开(公告)号：US10802516B2

    公开(公告)日：2020-10-13

    申请号：US16190523

    申请日：2018-11-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Adam S. El-Mansouri ,  Fuad Badrieh ,  Brent Keeth

    IPC: G05F1/10 ,  H01L25/065

    Abstract: Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit board that regulates a first voltage; a semiconductor device on the circuit board that receives the first voltage through a power line in the circuit board. The semiconductor device includes: a substrate on the circuit board, stacked via conductive balls, that receives the first voltage from the power line via the conductive balls; a plurality of dies on the semiconductor device, stacked via bumps, each die including, a first conductive via that receives the first voltage via the bumps; a plurality of pillars between adjacent dies and couple the first conductive vias of the adjacent dies; and a sense node switch circuit that selectively couples one first conductive via of one die among the plurality of dies to the regulator.

    MEMORY DEVICE INTERFACE AND METHOD
    100.
    发明申请
    MEMORY DEVICE INTERFACE AND METHOD 审中-公开

    公开(公告)号：US20200272560A1

    公开(公告)日：2020-08-27

    申请号：US16797618

    申请日：2020-02-21

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/02 ,  H01L25/065

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

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