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    Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices
    92.
    发明申请
    Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices 有权

    公开(公告)号：US20240431090A1

    公开(公告)日：2024-12-26

    申请号：US18821139

    申请日：2024-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4094 ,  H01L29/78

    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

    Apparatuses and methods for sense line architectures for semiconductor memories
    93.
    发明授权
    Apparatuses and methods for sense line architectures for semiconductor memories 有权

    公开(公告)号：US11715513B2

    公开(公告)日：2023-08-01

    申请号：US17573271

    申请日：2022-01-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toby D. Robbs ,  Charles L. Ingalls

    IPC: H10B12/00 ,  G11C11/4091 ,  G11C11/4097

    CPC classification number: G11C11/4091 ,  G11C11/4097 ,  H10B12/50

    Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.

    Integrated memory comprising secondary access devices between digit lines and primary access devices
    95.
    发明授权
    Integrated memory comprising secondary access devices between digit lines and primary access devices 有权

    公开(公告)号：US11450668B2

    公开(公告)日：2022-09-20

    申请号：US17324976

    申请日：2021-05-19

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: G11C11/24 ,  H01L27/108 ,  H01L29/78 ,  G11C11/4094 ,  G11C11/4091

    Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

    Driver leakage control
    96.
    发明授权
    Driver leakage control 有权

    公开(公告)号：US11342014B1

    公开(公告)日：2022-05-24

    申请号：US17306311

    申请日：2021-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Charles L. Ingalls

    IPC: G11C8/08 ,  G11C8/10

    Abstract: Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry.

    Half density ferroelectric memory and operation
    97.
    发明授权
    Half density ferroelectric memory and operation 有权

    公开(公告)号：US11250900B2

    公开(公告)日：2022-02-15

    申请号：US17001296

    申请日：2020-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: G11C11/22 ,  G11C7/06 ,  G11C7/00 ,  G11C7/14 ,  G11C11/4099 ,  G11C11/16 ,  G11C11/56

    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

    MEMORY ARRAYS WITH VERTICAL THIN FILM TRANSISTORS COUPLED BETWEEN DIGIT LINES
    99.
    发明申请
    MEMORY ARRAYS WITH VERTICAL THIN FILM TRANSISTORS COUPLED BETWEEN DIGIT LINES 有权

    公开(公告)号：US20210125661A1

    公开(公告)日：2021-04-29

    申请号：US17140540

    申请日：2021-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Scott J. Derner ,  Charles L. Ingalls

    IPC: G11C11/4097 ,  H01L27/108 ,  G11C11/4091 ,  H01L27/12

    Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

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