中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

148 records (took 0.021 seconds)

    DEDICATED COMMANDS FOR MEMORY OPERATIONS
    91.
    发明申请
    DEDICATED COMMANDS FOR MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20200082883A1

    公开(公告)日：2020-03-12

    申请号：US16128550

    申请日：2018-09-12

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

    IPC: G11C13/00 ,  G11C8/12

    Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

    PROVIDING ENERGY INFORMATION TO MEMORY
    92.
    发明申请
    PROVIDING ENERGY INFORMATION TO MEMORY 审中-公开

    公开(公告)号：US20200064903A1

    公开(公告)日：2020-02-27

    申请号：US16666975

    申请日：2019-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

    IPC: G06F1/3234 ,  G06F13/16 ,  G11C5/14

    Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

    TRANSACTION METADATA
    93.
    发明申请
    TRANSACTION METADATA 审中-公开

    公开(公告)号：US20190324843A1

    公开(公告)日：2019-10-24

    申请号：US15958401

    申请日：2018-04-20

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Paolo Amato ,  Danilo Caraccio

    IPC: G06F11/10 ,  G06F13/16 ,  G06F9/46

    Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES
    94.
    发明申请
    APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES 审中-公开

    公开(公告)号：US20190080733A1

    公开(公告)日：2019-03-14

    申请号：US16189865

    申请日：2018-11-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio

    IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10

    Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

    Systems and methods for providing file information in a memory system protocol
    95.
    发明授权
    Systems and methods for providing file information in a memory system protocol 有权

    公开(公告)号：US10175908B2

    公开(公告)日：2019-01-08

    申请号：US15862472

    申请日：2018-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

    IPC: G06F3/06

    Abstract: A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol. The commands include a write command with blocks of data to be stored in the memory device and contextual file system data for the blocks of data. The contextual file system data includes file metadata, file attributes, or both that identify an association of the one or more blocks of data with a file. The file is made up of the one or more blocks of data. The controller identifies the association of the one or more blocks of data with the file and executes the one or more commands, such that the one or more blocks of data are stored in the memory device with a placement based upon the association.

    APPARATUSES AND METHODS FOR VARIABLE LATENCY MEMORY OPERATIONS
    96.
    发明申请
    APPARATUSES AND METHODS FOR VARIABLE LATENCY MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20180349302A1

    公开(公告)日：2018-12-06

    申请号：US16058793

    申请日：2018-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

    IPC: G06F13/16 ,  G11C8/06 ,  G11C7/10 ,  G11C7/22

    Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

    Methods and apparatuses for executing a plurality of queued tasks in a memory
    97.
    发明授权
    Methods and apparatuses for executing a plurality of queued tasks in a memory 有权

    公开(公告)号：US10108372B2

    公开(公告)日：2018-10-23

    申请号：US14605593

    申请日：2015-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Graziano Mirichigni ,  Danilo Caraccio ,  Luca Porzio ,  Antonino Pollio

    IPC: G06F3/06 ,  G06F12/00

    Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.

Patent Agency Ranking