公开(公告)号：US11782727B2

公开(公告)日：2023-10-10

申请号：US16888198

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F9/4401 ,  G06F12/0877

CPC classification number: G06F9/4403 ,  G06F12/0877 ,  G06F2212/603

Abstract: Methods, systems, and devices for read prediction during a system boot procedure are described. A memory device may identify a command for a boot procedure and transfer data stored in a memory array to a cache of the memory device. In some cases, the memory device may prefetch data used during the boot procedure and thereby improve the latency of the boot procedure. When the memory device receives a command that requests data stored in the memory array as part of the boot procedure, the memory device may identify a cache hit based on prefetching the requested data before the command is received. In such cases, the memory device may retrieve the prefetched data from the cache.

公开(公告)号：US11763895B2

公开(公告)日：2023-09-19

申请号：US17873850

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

IPC: G11C16/04 ,  G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

CPC classification number: G11C16/30 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/0875 ,  G11C16/10 ,  G06F2212/603 ,  G11C16/0483

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US11755490B2

公开(公告)日：2023-09-12

申请号：US17122174

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Luca Porzio ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F12/0873 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0873 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0891 ,  G06F2212/7201

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

公开(公告)号：US20230259291A1

公开(公告)日：2023-08-17

申请号：US17651215

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Jonathan S. Parry ,  Reshmi Basu

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0632 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

公开(公告)号：US11720281B2

公开(公告)日：2023-08-08

申请号：US17119290

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

公开(公告)号：US20230229352A1

公开(公告)日：2023-07-20

申请号：US17579995

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Nicolas Soberanes ,  Ezra E. Hartz ,  Jonathan S. Parry ,  Bruce J. Ford ,  Joseph A. De La Cerda ,  Benjamin Rivera

IPC: G06F3/06 ,  G06F12/0811 ,  G06K9/62

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0679 ,  G06F12/0811 ,  G06K9/6256

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

公开(公告)号：US20230214294A1

公开(公告)日：2023-07-06

申请号：US17647700

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1417 ,  G06F11/142 ,  G06F12/0238

Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.

公开(公告)号：US20230214137A1

公开(公告)日：2023-07-06

申请号：US17736605

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.

公开(公告)号：US11416393B2

公开(公告)日：2022-08-16

申请号：US17219727

申请日：2021-03-31

Applicant: Micron Technology, Inc.

Inventor： Robert B. Eisenhuth ,  Jonathan S. Parry

IPC: G06F12/02 ,  G06F12/04

Abstract: A method for performing a copyback procedure is described. The method includes determining to move first encoded data from a first location in a memory die to a second location. In response to determining to move the first encoded data from the first location to the second location, a starting seed, which is associated with the first location, is combined with a destination seed, which is associated with the second location, to produce a combined seed. Based on the combined seed, the method determines a pseudorandom sequence based on the combined seed and a pseudorandom sequence table, wherein the pseudorandom sequence table maps seed values to pseudorandom sequences and the determined pseudorandom sequence maps to the combined seed in the pseudorandom sequence table. The method further combines the first encoded data with the pseudorandom sequence to produce second encoded data for storage in the second location.

公开(公告)号：US20220253226A1

公开(公告)日：2022-08-11

申请号：US17574044

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.