公开(公告)号：US20230269937A1

公开(公告)日：2023-08-24

申请号：US18108970

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H10B41/27 ,  H01L29/792 ,  H01L21/28 ,  H10B41/30 ,  H10B41/35 ,  H10B43/20 ,  H10B43/27 ,  H01L29/04 ,  H01L29/167 ,  H01L29/49 ,  H01L29/788

CPC classification number: H10B41/27 ,  H01L29/792 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/30 ,  H10B41/35 ,  H10B43/20 ,  H10B43/27 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

公开(公告)号：US11462544B2

公开(公告)日：2022-10-04

申请号：US16161381

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

公开(公告)号：US11456299B2

公开(公告)日：2022-09-27

申请号：US17318940

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220302015A1

公开(公告)日：2022-09-22

申请号：US17837923

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10 ,  G11C13/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1157

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US11444088B2

公开(公告)日：2022-09-13

申请号：US17070759

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： Hong Li ,  Ramaswamy Ishwar Venkatanarayanan ,  Sanh D. Tang ,  Erica L. Poelstra

IPC: H01L27/108 ,  H01L23/49 ,  H01L23/538 ,  G11C11/402 ,  H01L29/78 ,  H01L29/66

Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.

公开(公告)号：US20210265356A1

公开(公告)日：2021-08-26

申请号：US17318940

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10978554B2

公开(公告)日：2021-04-13

申请号：US16568504

申请日：2019-09-12

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kuo-Chen Wang

IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/108

Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.

公开(公告)号：US20210066306A1

公开(公告)日：2021-03-04

申请号：US16550917

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kirk D. Prall ,  Mitsunari Sukekawa

IPC: H01L27/108

Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

公开(公告)号：US10825815B2

公开(公告)日：2020-11-03

申请号：US15973707

申请日：2018-05-08

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Martin C. Roberts

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L21/265 ,  H01L27/11514 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/306 ,  H01L27/11597

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

公开(公告)号：US20200286906A1

公开(公告)日：2020-09-10

申请号：US16810009

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.