公开(公告)号：US10347634B2

公开(公告)日：2019-07-09

申请号：US15942938

申请日：2018-04-02

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Suraj Mathew

IPC: H01L27/105 ,  H01L21/768 ,  H01L21/74 ,  H01L27/108

Abstract: Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing the mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts is formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region.

公开(公告)号：US09111853B2

公开(公告)日：2015-08-18

申请号：US13840683

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/225 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L27/108

CPC classification number: H01L21/2257 ,  H01L21/26513 ,  H01L23/528 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41741 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

Abstract translation: 形成半导体器件结构的掺杂元素的方法包括形成具有分隔衬底的茎部的底切部分的沟槽。 杆部分在衬底的基部和衬底材料的较宽部分之间延伸。 包括掺杂剂的载体材料至少在沟槽的底切部分中的茎的侧面上形成。 掺杂剂从载体材料扩散到茎中。 因此，衬底的窄茎部分掺杂有目标掺杂剂递送方法。 掺杂的茎可以形成或者结合在半导体器件结构的掩埋的，掺杂的导电元件中，诸如存储器阵列的数字线。 还公开了相关的半导体器件结构。

公开(公告)号：US09070767B2

公开(公告)日：2015-06-30

申请号：US14079821

申请日：2013-11-14

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/108 ,  H01L29/66 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/7827 ,  H01L21/76232 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666

Abstract: Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region.

Abstract translation: 垂直存储器件包括垂直晶体管，在阵列区域中沿第一方向延伸的掩埋数字线以及沿与第一方向不同的第二方向延伸的字线。 字线端区域中的字线的部分具有大于阵列区域中的字线的部分的第二垂直长度的第一垂直长度。 还公开了包括阵列区域中的垂直晶体管，在第一方向上延伸的埋入数字线以及字线的装置。 每个字线在垂直于第一方向的第二方向上延伸，形成在至少一些垂直晶体管的侧壁的至少一部分上方，并且在字线端部区域中垂直地具有大约等于或等于 大于其在阵列区域中的深度。

公开(公告)号：US20150014766A1

公开(公告)日：2015-01-15

申请号：US14502978

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

公开(公告)号：US08871589B2

公开(公告)日：2014-10-28

申请号：US14030880

申请日：2013-09-18

Applicant: Micron Technology, Inc.

Inventor： Lars P Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

公开(公告)号：US20140264754A1

公开(公告)日：2014-09-18

申请号：US13840683

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Surthi

IPC: H01L21/22 ,  H01L23/18

CPC classification number: H01L21/2257 ,  H01L21/26513 ,  H01L23/528 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41741 ,  H01L29/66666 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.

Abstract translation: 形成半导体器件结构的掺杂元素的方法包括形成具有分隔衬底的茎部的底切部分的沟槽。 杆部分在衬底的基部和衬底材料的较宽部分之间延伸。 包括掺杂剂的载体材料至少在沟槽的底切部分中的茎的侧面上形成。 掺杂剂从载体材料扩散到茎中。 因此，衬底的窄茎部分掺杂有目标掺杂剂递送方法。 掺杂的茎可以形成或者结合在半导体器件结构的掩埋的，掺杂的导电元件中，诸如存储器阵列的数字线。 还公开了相关的半导体器件结构。