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公开(公告)号：US11182237B1
公开(公告)日：2021-11-23
申请号：US17000062
申请日：2020-08-21
摘要： A processing device, operatively coupled with the memory device, is configured to perform an operation on a page of a plurality of pages of a data unit of the memory device to modify data on the page. The processing device also determines a first operation execution time of the page upon performing the operation on the page of the data unit. The processing device further determines whether the first operation execution time satisfies a condition that is based on a predetermined second operation execution time, the predetermined second operation execution time is indicative of lack of defect in at least one other data unit. Lastly, responsive to determining that the first operation execution time satisfies the condition, the processing device performs a scan operation of at least a subset of the plurality of pages of the data unit to decide whether the data unit has a defect.
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公开(公告)号：US20210327514A1
公开(公告)日：2021-10-21
申请号：US17361259
申请日：2021-06-28
摘要： An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.
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公开(公告)号：US11137808B2
公开(公告)日：2021-10-05
申请号：US16119541
申请日：2018-08-31
IPC分类号： G11C11/06 , G06F1/20 , G06F1/3234 , G11C11/56
摘要： A processing device in a memory system receives a data access request identifying a memory cell in a first segment of the memory system comprising at least a portion of at least one memory device. The processing device determines a temperature difference between a current temperature associated with the memory cell and a baseline temperature of the memory system and identifies a temperature compensation value specific to the first segment of the memory system, the temperature compensation value corresponding to the temperature difference. The processing device adjusts, based on an amount represented by the temperature compensation value, an access control voltage applied to the memory cell.
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公开(公告)号：US11068197B2
公开(公告)日：2021-07-20
申请号：US16460401
申请日：2019-07-02
发明人： Kishore Kumar Muchherla , Peter Sean Feeley , Ashutosh Malshe , Sampath Ratnam , Harish Reddy Singidi , Vamsi Pavan Rayaprolu
IPC分类号： G06F3/06
摘要： A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US11023177B2
公开(公告)日：2021-06-01
申请号：US16909503
申请日：2020-06-23
发明人： Gianni Stephen Alsasua , Karl D. Schuh , Ashutosh Malshe , Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Sampath Ratnam , Harish Reddy Singidi , Renato Padilla, Jr.
IPC分类号： G11C16/04 , G06F3/06 , G06F12/1009 , G11C16/34 , G11C16/26
摘要： A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.
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公开(公告)号：US20200293203A1
公开(公告)日：2020-09-17
申请号：US16889712
申请日：2020-06-01
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Kishore Kumar Muchherla , Harish R. Singidi , Ashutosh Malshe , Gianni S. Alsasua
IPC分类号： G06F3/06
摘要： A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.
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公开(公告)号：US20200251162A1
公开(公告)日：2020-08-06
申请号：US16855579
申请日：2020-04-22
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号： G11C11/406 , G06F13/16
摘要： Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.
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公开(公告)号：US20200159410A1
公开(公告)日：2020-05-21
申请号：US16195743
申请日：2018-11-19
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Harish R. Singidi , Ashutosh Malshe , Kishore Kumar Muchherla
IPC分类号： G06F3/06
摘要： A region of a memory component is determined to include a type of memory. A frequency to perform an operation on the region of the memory component is determined based on the type of memory. The operation is performed on a memory cell at the region of the memory component at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
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公开(公告)号：US20200098421A1
公开(公告)日：2020-03-26
申请号：US16138115
申请日：2018-09-21
发明人： Gianni Stephen Alsasua , Harish Reddy Singidi , Kishore Kumar Muchherla , Sampath Ratnam , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Renato Padilla, JR.
IPC分类号： G11C11/406 , G06F13/16
摘要： Devices and techniques for temperature informed memory refresh are described herein. Temperature data can be updated in response to a memory component write performed under an extreme temperature. Here, the write is performed on a memory component element in the memory component. The memory component element can be sorted above other memory component elements in the memory component based on the temperature data. Once sorted to the top of these memory component elements, a refresh can be performed the memory component element.
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100.发明申请公开(公告)号：US20190341117A1
公开(公告)日：2019-11-07
申请号：US16514861
申请日：2019-07-17
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Peter Feeley , Kishore Kumar Muchherla , Renato C. Padilla , Shane Nowell
摘要： A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
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