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121 条记录 (耗时 0.03 秒)

    Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes
    95.
    发明申请
    Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes 失效
    集成电路芯片利用由碳纳米管形成的具有取向的圆柱形空隙的电介质层

    公开(公告)号：US20060128137A1

    公开(公告)日：2006-06-15

    申请号：US11008800

    申请日：2004-12-09

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

    IPC分类号： H01L21/4763

    CPC分类号： B82Y10/00 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

    摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

    摘要翻译： 集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。 优选地，通过首先通过在表面上沉积常规电介质以填充碳纳米管之间的区域，然后通过将碳纳米管去除以形成多个相对较长的薄碳纳米管，形成集成电路晶片的表面，形成空隙 产生代替碳纳米管的空隙。 由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。 使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

    Borderless contact structures
    97.
    发明申请
    Borderless contact structures 失效

    公开(公告)号：US20060024940A1

    公开(公告)日：2006-02-02

    申请号：US10710675

    申请日：2004-07-28

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/11 ,  H01L27/1104

    摘要： A borderless contact structure and method of fabricating the structure, the method including: (a) providing a substrate; (b) forming a polysilicon line on the substrate, the polysilicon line having sidewalls; (c) forming an insulating sidewall layer on the sidewalls of the polysilicon line; (d) removing a portion of the polysilicon line and a corresponding portion of the insulating sidewall layer in a contact region of the polysilicon line; and (e) forming a silicide layer on the sidewall of the polysilicon line in the contact region. Also an SRAM cell using the borderless contact structure and a method of fabricating the SRAM cell.

    Formation of a disposable spacer to post dope a gate conductor
    99.
    发明申请
    Formation of a disposable spacer to post dope a gate conductor 失效
    一次性间隔件的形成以喷涂一个栅极导体

    公开(公告)号：US20050145958A1

    公开(公告)日：2005-07-07

    申请号：US10752386

    申请日：2004-01-06

    申请人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    发明人： David Horak ,  Toshiharu Furukawa ,  Akihisa Sekiguchi

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/6653 ,  H01L21/28035 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second layers. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.

    摘要翻译： 提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。 该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。 后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。 在第一栅极层和第二层周围形成脂肪间隔物。 去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。