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177 条记录 (耗时 0.036 秒)

    Engineered metal gate electrode
    91.
    发明授权
    Engineered metal gate electrode 有权
    工程金属栅电极

    公开(公告)号：US07033888B2

    公开(公告)日：2006-04-25

    申请号：US10806117

    申请日：2004-03-23

    申请人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

    发明人： James N. Pan ,  Paul R. Besser ,  Christy Woo ,  Minh Van Ngo ,  Jinsong Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L29/4966

    摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

    摘要翻译： 形成具有固有电场的金属栅电极，以改变晶体管的功函数和阈值电压。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积一层或多层氮化钽，使氮含量从邻近栅介质层的层的底部向上增加。 其他实施例包括通过掺杂一个或多个金属层并形成金属合金来形成本征电场以控制功函数。 实施例还包括在形成金属栅电极时使用阻挡层。

    Ultra-uniform silicides in integrated circuit technology
    92.
    发明授权
    Ultra-uniform silicides in integrated circuit technology 有权
    集成电路技术中超均匀的硅化物

    公开(公告)号：US07005376B2

    公开(公告)日：2006-02-28

    申请号：US10615086

    申请日：2003-07-07

    申请人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    发明人： Robert J. Chiu ,  Jeffrey P. Patton ,  Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28518

    摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

    摘要翻译： 提供一种集成电路的形成方法和结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

    Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation
    93.
    发明授权
    Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon layer and in-situ anneal to reduce silicon consumption during salicidation 失效
    在具有沉积硅层的半导体晶片中形成超浅结的方法和原位退火以减少在盐化期间的硅消耗

    公开(公告)号：US06835656B1

    公开(公告)日：2004-12-28

    申请号：US10163459

    申请日：2002-06-07

    申请人： Paul R. Besser ,  Minh Van Ngo

    发明人： Paul R. Besser ,  Minh Van Ngo

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/28525

    摘要： A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal silicide regions are formed on the gate and source/drain junctions. Amorphous silicon is then deposited in a layer on the high resistivity metal silicide regions by high density plasma chemical vapor deposition. The deposition of the amorphous-silicon is at an elevated temperature which causes transforming of the high resistivity metal silicide regions to low resistivity metal silicide regions on the gate and source/drain junctions. The deposited amorphous-silicon acts as a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to the low resistivity metal silicide.

    摘要翻译： 用于在半衰期期间形成超浅结的方法，其中在硅化过程中硅消耗减少，在盐析过程中提供额外的硅。 在半导体器件中形成栅极和源极/漏极结之后，在栅极和源极/漏极结上形成高电阻金属硅化物区域。 然后通过高密度等离子体化学气相沉积将非晶硅沉积在高电阻率金属硅化物区域的一层中。 非晶硅的沉积处于升高的温度，这导致高电阻率金属硅化物区域转变为栅极和源极/漏极结上的低电阻率金属硅化物区域。 沉积的非晶硅在高电阻率金属硅化物向低电阻率金属硅化物的转变期间充当硅源，用作扩散物质。

    Pre-cleaning for silicidation in an SMOS process
    94.
    发明授权
    Pre-cleaning for silicidation in an SMOS process 有权
    在SMOS工艺中预硅化硅化

    公开(公告)号：US06811448B1

    公开(公告)日：2004-11-02

    申请号：US10619879

    申请日：2003-07-15

    申请人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

    发明人： Eric N. Paton ,  Paul R. Besser ,  Qi Xiang

    IPC分类号： H01L21302

    CPC分类号： H01L21/02054 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/28518 ,  H01L29/665

    摘要： A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

    摘要翻译： 制造系统利用用于从晶片顶表面去除自然氧化物的协议。 暴露于等离子体，例如含有氢气和氩气的等离子体可从顶表面除去天然氧化物，而不会引起过量的锗污染。 该方案可以使用氟化氢浸渍。 在使用等离子体之前可以使用氟化氢浸渍。 该协议允许在SMOS器件中更好的硅化。

    Metal silicide gate transistors
    96.
    发明授权
    Metal silicide gate transistors 有权
    金属硅化物晶体管

    公开(公告)号：US06602781B1

    公开(公告)日：2003-08-05

    申请号：US09734207

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L2144

    CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

    摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

    摘要翻译： 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

    Nitrogen-plasma treatment for reduced nickel silicide bridging
    99.
    发明授权
    Nitrogen-plasma treatment for reduced nickel silicide bridging 有权
    氮等离子体处理用于还原硅化镍桥接

    公开(公告)号：US06465349B1

    公开(公告)日：2002-10-15

    申请号：US09679372

    申请日：2000-10-05

    申请人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

    发明人： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Paul R. Besser ,  Robert A. Huertas

    IPC分类号： H01L2144

    CPC分类号： H01L29/665 ,  H01L21/3115 ,  Y10S257/90

    摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

    摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面以形成具有减少的自由硅的表面区域，防止沿栅极电极的硅化镍层与氮化硅侧壁间隔物的源极/漏极区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。

    Silicide gate transistors
    100.
    发明授权
    Silicide gate transistors 有权
    硅化物栅极晶体管

    公开(公告)号：US06465309B1

    公开(公告)日：2002-10-15

    申请号：US09734185

    申请日：2000-12-12

    申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545

    摘要： A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

    摘要翻译： 半导体结构及其制造方法提供由氧氮化物形成的栅极电介质或形成在凹部内的氮化物/氧化物堆叠。 非晶硅沉积在凹槽内的栅极电介质上，金属沉积在非晶硅上。 退火工艺在栅极电介质的凹槽内形成金属硅化物栅极。 可以选择更宽范围的金属材料，因为由氮氧化物或氮化物/氧化物堆叠形成的栅极电介质在硅化过程中保持稳定。 金属硅化物栅极显着降低了栅极和栅极端子之间的薄层电阻。