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177 条记录 (耗时 0.028 秒)

    Method of selectively alloying interconnect regions by deposition process
    4.
    发明授权
    Method of selectively alloying interconnect regions by deposition process 有权
    通过沉积工艺选择合金化互连区域的方法

    公开(公告)号：US06656834B1

    公开(公告)日：2003-12-02

    申请号：US09884027

    申请日：2001-06-20

    申请人： Paul R. Besser ,  Larry Zhao

    发明人： Paul R. Besser ,  Larry Zhao

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

    摘要翻译： 金属互连结构及其制造方法提供了在电介质层中对通孔进行排列的合金元素层。 因此，合金元素层被插入临界电迁移破坏部位，即位于底层金属的通孔下方的快速扩散部位。 一旦在通孔中进行铜填充，退火步骤允许合金元素进入固体溶液，铜通过其中和周围。 铜线中通孔底部的合金元素和铜的固溶体提高了结构的电迁移可靠性。

    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices
    6.
    发明授权
    Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices 有权
    阻挡金属层反向电镀以提高铜互连器件的电迁移性能

    公开(公告)号：US06261963B1

    公开(公告)日：2001-07-17

    申请号：US09611729

    申请日：2000-07-07

    申请人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    发明人： Larry Zhao ,  Paul R. Besser ,  Eric M. Apelgren ,  Christian Zistl ,  Jonathan B. Smith

    IPC分类号： H01L21302

    CPC分类号： H01L21/76873 ,  H01L21/2885 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  Y10S438/927

    摘要： A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.

    摘要翻译： 提供了一种用于形成导电互连的方法，所述方法包括在结构层上形成第一介电层，在第一介电层中形成第一开口，并在第一开口中形成第一导电结构。 该方法还包括在第一介电层之上和第一导电结构之上形成第二电介质层，在第二导电结构的至少一部分上方的第二电介质层中形成第二开口，第二开口具有侧表面和 并且在侧表面和底表面上的第二开口中形成至少一个阻挡金属层。 此外，该方法包括从底表面去除至少一个阻挡金属层的一部分，以及在第二开口中形成第二导电结构，第二导电结构与第一导电结构的至少一部分接触。 该方法还包括通过使第二导电结构和第一导电结构退火来形成导电互连。

    Multi-layer barrier layer for interconnect structure
    7.
    发明授权
    Multi-layer barrier layer for interconnect structure 有权
    用于互连结构的多层阻挡层

    公开(公告)号：US08728931B2

    公开(公告)日：2014-05-20

    申请号：US13553977

    申请日：2012-07-20

    申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

    摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

    Method to reduce MOL damage on NiSi
    9.
    发明授权
    Method to reduce MOL damage on NiSi 有权
    减少NiSi上MOL损伤的方法

    公开(公告)号：US07994038B2

    公开(公告)日：2011-08-09

    申请号：US12366378

    申请日：2009-02-05

    申请人： Karthik Ramani ,  Paul R. Besser

    发明人： Karthik Ramani ,  Paul R. Besser

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/458 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

    摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.

    摘要翻译： 晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。 实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。 实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。 然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。 铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

    Semiconductor device and method of manufacturing a semiconductor device
    10.
    发明授权
    Semiconductor device and method of manufacturing a semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US07910996B2

    公开(公告)日：2011-03-22

    申请号：US12496133

    申请日：2009-07-01

    申请人： Paul R. Besser ,  Scott D. Luning

    发明人： Paul R. Besser ,  Scott D. Luning

    IPC分类号： H01L29/12

    CPC分类号： H01L29/66628 ,  H01L29/66772

    摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

    摘要翻译： 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。