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    METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR
    91.
    发明申请
    METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR 审中-公开
    减少图案识别处理器功耗的方法和装置

    公开(公告)号：US20170068707A1

    公开(公告)日：2017-03-09

    申请号：US15357593

    申请日：2016-11-21

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown

    IPC: G06F17/30 ,  G06F1/32

    CPC classification number: G06F17/30516 ,  G06F1/3296 ,  G06F17/30985 ,  G06K9/00986 ,  Y02D10/45

    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

    Abstract translation: 提供了用于降低图案识别处理器中的功耗的装置和方法。 功率控制电路可以耦合到编程状态机的块，以在模式搜索期间能够选择性地激活和去激活块。 如果模式搜索在该块中不再有效并且在模式搜索需要时被激活，则块可以被去激活。 另外，可以基于正在搜索的数据流的标识符来停用该块。 不用于任何编程状态机的过多块可能被禁用，使得它们在存储器循环期间不被刷新。

    MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS
    92.
    发明申请
    MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS 审中-公开
    模式识别处理器的多层次分层路由矩阵

    公开(公告)号：US20160239462A1

    公开(公告)日：2016-08-18

    申请号：US15137877

    申请日：2016-04-25

    Applicant: Micron Technology, Inc.

    Inventor： Harold B Noyes ,  David R. Brown

    IPC: G06F15/80 ,  G06N5/00

    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

    Abstract translation: 提供了用于模式识别处理器的多级分层路由矩阵。 一个这样的路由矩阵可以包括在矩阵的层内和之间的一个或多个可编程和/或不可编程的连接。 这些连接可以将路由线路耦合到特征单元，组，行，块或模式识别处理器的任何其他组件的布置。

    BOOLEAN LOGIC IN A STATE MACHINE LATTICE
    94.
    发明申请
    BOOLEAN LOGIC IN A STATE MACHINE LATTICE 有权
    BOOLEAN逻辑在一个状态机床

    公开(公告)号：US20150365091A1

    公开(公告)日：2015-12-17

    申请号：US14832543

    申请日：2015-08-21

    Applicant: Micron Technology, Inc.

    Inventor： Harold B. Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

    IPC: H03K19/177 ,  G05B19/045

    CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

    Abstract translation: 公开了方法和装置，其中包括有限状态机格的装置。 晶格可以包括可编程布尔逻辑单元，其可以被编程为在数据流上执行各种逻辑功能。 可编程性包括对布尔逻辑单元的第一输入的反转，布尔逻辑单元的最后输出的反转，以及选择与门或或门作为布尔逻辑单元的最终输出。 布尔逻辑单元还包括数据电路的结尾，该数据电路被配置为仅在布尔逻辑单元接收到表示数据流结束的数据结束后才输出布尔逻辑单元。

    METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
    95.
    发明申请
    METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE 有权
    用于提供状态机发动机接收的数据的方法和装置

    公开(公告)号：US20140279776A1

    公开(公告)日：2014-09-18

    申请号：US14065168

    申请日：2013-10-28

    Applicant: Micron Technology, Inc.

    Inventor： David R. Brown ,  Harold B. Noyes ,  Inderjit S. Bains

    IPC: G06N3/02

    CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

    Abstract translation: 装置可以包括被配置为从处理器接收数据流的第一部分的第一状态机引擎和被配置为从处理器接收数据流的第二部分的第二状态机引擎。 该装置包括缓冲器接口，该缓冲器接口被配置为使能第一和第二状态机引擎之间的数据传输。 缓冲器接口包括耦合到第一和第二状态机引擎的接口数据总线。 缓冲器接口被配置为在第一和第二状态机引擎之间提供数据。

    COMBINED PARALLEL/SERIAL STATUS REGISTER READ
    96.
    发明申请
    COMBINED PARALLEL/SERIAL STATUS REGISTER READ 有权

    公开(公告)号：US20130073803A1

    公开(公告)日：2013-03-21

    申请号：US13677771

    申请日：2012-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Brian Huber ,  Frank Ross ,  David R. Brown

    IPC: G06F12/00

    CPC classification number: G11C7/1063 ,  G11C7/1045 ,  G11C7/1051 ,  G11C11/4078

    Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

    Synchronous input buffer control using a write shifter
    98.
    发明授权
    Synchronous input buffer control using a write shifter 有权

    公开(公告)号：US12223999B2

    公开(公告)日：2025-02-11

    申请号：US17853517

    申请日：2022-06-29

    Applicant: Micron Technology, Inc.

    Inventor： William Chad Waldrop ,  David R. Brown ,  Guy S. Perry, IV

    IPC: G11C11/4093

    Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

    Synchronous Input Buffer Control Using a Write Shifter
    100.
    发明公开
    Synchronous Input Buffer Control Using a Write Shifter 审中-公开

    公开(公告)号：US20240005980A1

    公开(公告)日：2024-01-04

    申请号：US17853517

    申请日：2022-06-29

    Applicant: Micron Technology, Inc.

    Inventor： William Chad Waldrop ,  David R. Brown ,  Guy S. Perry, IV

    IPC: G11C11/4093

    CPC classification number: G11C11/4093

    Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.

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