Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
    92.
    发明授权
    Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine 有权
    并行地接收数据流并将第一部分数据提供给第一状态机引擎,将第二部分提供给第二状态机

    公开(公告)号:US09448965B2

    公开(公告)日:2016-09-20

    申请号:US14065168

    申请日:2013-10-28

    CPC classification number: G06F13/4027 G06F9/4498 G06F15/7867 G06N3/08

    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

    Abstract translation: 装置可以包括被配置为从处理器接收数据流的第一部分的第一状态机引擎和被配置为从处理器接收数据流的第二部分的第二状态机引擎。 该装置包括缓冲器接口,该缓冲器接口被配置为使能第一和第二状态机引擎之间的数据传输。 缓冲器接口包括耦合到第一和第二状态机引擎的接口数据总线。 缓冲器接口被配置为在第一和第二状态机引擎之间提供数据。

    RESULTS GENERATION FOR STATE MACHINE ENGINES
    94.
    发明申请
    RESULTS GENERATION FOR STATE MACHINE ENGINES 有权
    国家机器发动机的产生

    公开(公告)号:US20150324129A1

    公开(公告)日:2015-11-12

    申请号:US14756000

    申请日:2015-06-30

    Abstract: A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis of data. The storage element is also configured to store the result in a particular portion of the storage element based on a characteristic of the result. The storage element is additionally configured to store a result indicator corresponding to the result. Other state machine engines and methods are also disclosed.

    Abstract translation: 状态机引擎包括诸如(例如,匹配)结果存储器的存储元件。 存储元件被配置为接收数据分析的结果。 存储元件还被配置为基于结果的特性将结果存储在存储元件的特定部分中。 存储元件还被配置为存储对应于结果的结果指示符。 还公开了其他状态机引擎和方法。

    Methods and systems to accomplish variable width data input
    95.
    发明授权
    Methods and systems to accomplish variable width data input 有权
    完成可变宽度数据输入的方法和系统

    公开(公告)号:US09164940B2

    公开(公告)日:2015-10-20

    申请号:US14245703

    申请日:2014-04-04

    Inventor: Harold B Noyes

    CPC classification number: G06F13/385 G06F13/4018

    Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.

    Abstract translation: 公开了用于将可变宽度数据输入到模式识别处理器的方法和系统。 可变宽度数据输入方法可以包括通过具有第一宽度的数据总线接收字节,并且接收指示一个或多个字节中的每一个的有效性的一个或多个信号。 有效字节可以顺序地提供给8位宽数据流中的模式识别处理器。 在一个实施例中,系统可以包括一个或多个地址线,其被配置为提供指示通过数据总线传送的字节的有效性的一个或多个信号。 系统可以包括缓冲器和控制逻辑以顺序地处理有效字节。

    METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER
    96.
    发明申请
    METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER 有权
    具有自选择总线解码器的设备的方法和系统

    公开(公告)号:US20130198433A1

    公开(公告)日:2013-08-01

    申请号:US13801447

    申请日:2013-03-13

    Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

    Abstract translation: 公开了一种方法和装置,其中包括一个自选总线解码器的装置。 在一些实施例中,设备可以耦合到微控制器,并且自选择总线解码器可以确定外围设备对来自微控制器的请求的响应。 在另一个实施例中,设备可以包括总线转换器和自选总线解码器。 总线转换器可以被配置为在来自多个不同类型的总线中选定的一个的信号之间进行转换。 微控制器可以耦合到总线转换器的多个不同类型的总线中选定的一个。

    ADAPTIVE CONTENT INSPECTION
    98.
    发明申请

    公开(公告)号:US20250148312A1

    公开(公告)日:2025-05-08

    申请号:US19018107

    申请日:2025-01-13

    Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.

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