公开(公告)号：US11948639B2

公开(公告)日：2024-04-02

申请号：US17368395

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H10B41/27 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240081070A1

公开(公告)日：2024-03-07

申请号：US17929965

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

Abstract: Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.

公开(公告)号：US20240074202A1

公开(公告)日：2024-02-29

申请号：US17897350

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/1157 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11578

CPC classification number: H01L27/1157 ,  H01L21/30608 ,  H01L21/3086 ,  H01L27/11578

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. An anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. The anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. Individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US20240074182A1

公开(公告)日：2024-02-29

申请号：US17897399

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. Methods are also disclosed.

公开(公告)号：US20240071496A1

公开(公告)日：2024-02-29

申请号：US17897460

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

公开(公告)号：US11915974B2

公开(公告)日：2024-02-27

申请号：US17227734

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shuangqiang Luo ,  Alyssa N. Scarbrough

IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: Integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. The islands comprise multiple different composition materials directly above the conductor material. Apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. Other embodiments, including methods, are disclosed.

公开(公告)号：US11910596B2

公开(公告)日：2024-02-20

申请号：US17223254

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

公开(公告)号：US11903211B2

公开(公告)日：2024-02-13

申请号：US17647238

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/41

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20240032295A1

公开(公告)日：2024-01-25

申请号：US17813847

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11543 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L27/11543 ,  H01L29/40117

Abstract: Electronic devices comprising a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, tiers of alternating conductive materials and insulative materials adjacent to the source contact, pillars extending through the tiers and the source contact and into the source stack, a slit structure extending through the tiers and the source contact, and an implant structure extending within the slit structure and into the source stack. Related methods and systems are also disclosed.

公开(公告)号：US20240032294A1

公开(公告)日：2024-01-25

申请号：US17813818

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: An electronic device comprising a source stack comprising one or more conductive materials, and an oxide fill region within an upper portion of the source stack. A source contact is adjacent to the source stack and the oxide fill region, and a doped semiconductive material is adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material, and pillars extend through the tiers, the doped semiconductive material, and the source contact and into the source stack. Additional electronic devices are also disclosed, as are related methods and electronic systems.