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    Erasing memory
    91.
    发明授权
    Erasing memory 有权

    公开(公告)号：US11514987B2

    公开(公告)日：2022-11-29

    申请号：US17228807

    申请日：2021-04-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

    Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

    Methods of forming microelectronic devices, and related microelectronic devices and electronic systems
    95.
    发明授权
    Methods of forming microelectronic devices, and related microelectronic devices and electronic systems 有权

    公开(公告)号：US11282815B2

    公开(公告)日：2022-03-22

    申请号：US16742485

    申请日：2020-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

    IPC: H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/00 ,  H01L25/00

    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

    MEMORY DEVICE INCLUDING DATA LINES ON MULTIPLE DEVICE LEVELS
    96.
    发明申请
    MEMORY DEVICE INCLUDING DATA LINES ON MULTIPLE DEVICE LEVELS 有权

    公开(公告)号：US20210193570A1

    公开(公告)日：2021-06-24

    申请号：US16723758

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Paolo Tessariol ,  Aaron Yip ,  Naveen Kaushik

    IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/768

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure located over and in electrical contact with the first pillar; a second conductive structure extending in the first direction, the second conductive structure located over and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line located on a first level of the apparatus and extending in a second direction, the first data line located over the first conductive structure and in electrical contact with the first conductive structure; and a second data line located on a second level of the apparatus and extending in the second direction, the second data line located over the second conductive structure and in electrical contact with the second conductive structure.

    Integrated Structures, Capacitors and Methods of Forming Capacitors
    99.
    发明申请
    Integrated Structures, Capacitors and Methods of Forming Capacitors 审中-公开

    公开(公告)号：US20190341266A1

    公开(公告)日：2019-11-07

    申请号：US16514928

    申请日：2019-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Eric Freeman ,  Paolo Tessariol

    IPC: H01L21/311 ,  H01L27/11582 ,  H01L49/02 ,  H01L23/522

    Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

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