公开(公告)号：US4977435A

公开(公告)日：1990-12-11

申请号：US264785

申请日：1988-10-31

申请人： Toshiyuki Yoshimura ,  Eiji Takeda ,  Hideyuki Matsuoka ,  Yasuo Igura

发明人： Toshiyuki Yoshimura ,  Eiji Takeda ,  Hideyuki Matsuoka ,  Yasuo Igura

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/812

CPC分类号： B82Y10/00 ,  H01L29/66977 ,  H01L29/7831 ,  H01L29/8124 ,  H01L2924/0002

摘要： A semiconductor field effect transistor is provided which permits controlling of the phase of carriers between a source region and a drain region formed in a first semiconductor layer. Such control can be used to modulate characteristics such as the electric conductivity and drain current of the transistor. To accomplish this control, a gate electrode is formed over a portion of said first semiconductor layer between the source and drain regions. The gate electrode splits to form first and second branches at a first location adjacent to the source region. These first and second branches subsequently rejoin one another at a second location adjacent to said drain region. When a potential is applied to the gate electrode, it will produce first and second two-dimensional carriers conduction paths at a surface of the portion of the first semiconductor layer under the first and second branches. An arrangement is provided for modifying the phase of carriers passing through the first conduction path relative to the phase of carriers passing through the second conduction path to produce a phase difference for carriers received at the drain region through said first and second conduction paths.

摘要翻译： 提供一种半导体场效应晶体管，其允许控制在第一半导体层中形成的源区和漏区之间的载流子相。 这种控制可用于调制诸如晶体管的导电性和漏极电流的特性。 为了实现这种控制，在源极和漏极区域之间的所述第一半导体层的一部分上形成栅电极。 栅极电极在与源极区域相邻的第一位置处分开形成第一和第二分支。 这些第一和第二分支随后在与所述漏极区相邻的第二位置处彼此重合。 当电位施加到栅电极时，它将在第一和第二分支下的第一半导体层的部分的表面处产生第一和第二二维载流子传导路径。 提供一种用于修改通过第一导电路径的载流子相对于穿过第二导电路径的载流子相的相位的布置，以产生通过所述第一和第二导电路径在漏极区域接收的载流子的相位差。

公开(公告)号：US07221056B2

公开(公告)日：2007-05-22

申请号：US10871282

申请日：2004-06-21

申请人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

发明人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

IPC分类号： H01L23/495

CPC分类号： H01L21/02063 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process for a semiconductor integrated circuit device prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The metal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

摘要翻译： 半导体集成电路器件的制造工艺防止金属布线和硼掺杂的硅插件在其上形成的MOS晶体管的热处理中发生反应，并降低接触电阻上升的可能性。 金属硼化物形成在金属布线上的位于层间绝缘膜的开口底部的露出的金属表面上。 为了促进这种金属硼化物的形成，用氨水溶液除去残留在金属表面上的金属氧化物。 金属表面用高能紫外线照射，以除去残留在开口中的有机物，并有助于氨水溶液除去金属氧化物。

公开(公告)号：US20060148135A1

公开(公告)日：2006-07-06

申请号：US11368603

申请日：2006-03-07

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/50

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US06903966B2

公开(公告)日：2005-06-07

申请号：US10863748

申请日：2004-06-09

申请人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

发明人： Takeshi Sakata ,  Satoru Hanzawa ,  Hideyuki Matsuoka ,  Katsuro Watanabe ,  Kenchi Ito

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  G11C11/00

CPC分类号： H01L27/226 ,  B82Y10/00 ,  G11C11/16

摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

摘要翻译： 公开了一种快速，高度集成和高可靠性的磁阻随机存取存储器（MRAM）和使用MRAM的半导体器件。 半导体器件使用存储单元执行MRAM的读出操作，用于通过使用具有高S / N比的磁性隧道结（MTJ）元件的磁阻的变化来存储信息。 每个存储单元包括MTJ元件和双极晶体管。 通过选择字线，通过双极晶体管放大在目标存储单元的MTJ元件中流动的电流并将放大的电流输出到相关联的读取数据线来执行读出操作。

公开(公告)号：US20050117392A1

公开(公告)日：2005-06-02

申请号：US10931041

申请日：2004-09-01

申请人： Jun Hayakawa ,  Hideyuki Matsuoka

发明人： Jun Hayakawa ,  Hideyuki Matsuoka

IPC分类号： G11C11/15 ,  G11C11/14 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C11/16

摘要： A magnetic nonvolatile memory cell includes a C-MOSFET, a spin torque magnetization inversion layer and a tunneling magnetoresistive layer arranged in this order. The memory cell has the function of spin torque magnetization inversion and consumes very low power. A random access memory includes a plurality of the memory cells.

摘要翻译： 磁性非易失性存储单元包括依次布置的C-MOSFET，自旋转矩磁化反转层和隧道磁阻层。 存储单元具有自旋转矩磁化反转的功能，并且消耗非常低的功率。 随机存取存储器包括多个存储单元。

公开(公告)号：US20050073051A1

公开(公告)日：2005-04-07

申请号：US10871282

申请日：2004-06-21

申请人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

发明人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/02063 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process for a semiconductor integrated circuit device which prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The meal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

摘要翻译： 一种用于半导体集成电路器件的制造方法，其防止金属布线和硼掺杂硅插塞之间在其上形成的MOS晶体管的热处理中发生反应，并降低接触电阻上升的可能性。 金属硼化物形成在金属布线上的位于层间绝缘膜的开口底部的露出的金属表面上。 为了促进这种金属硼化物的形成，用氨水溶液除去残留在金属表面上的金属氧化物。 用高能量紫外线照射餐面，以除去残留在开口中的有机物质，并利用氨水溶液去除金属氧化物。