公开(公告)号：US07221056B2

公开(公告)日：2007-05-22

申请号：US10871282

申请日：2004-06-21

申请人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

发明人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

IPC分类号： H01L23/495

CPC分类号： H01L21/02063 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process for a semiconductor integrated circuit device prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The metal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

摘要翻译： 半导体集成电路器件的制造工艺防止金属布线和硼掺杂的硅插件在其上形成的MOS晶体管的热处理中发生反应，并降低接触电阻上升的可能性。 金属硼化物形成在金属布线上的位于层间绝缘膜的开口底部的露出的金属表面上。 为了促进这种金属硼化物的形成，用氨水溶液除去残留在金属表面上的金属氧化物。 金属表面用高能紫外线照射，以除去残留在开口中的有机物，并有助于氨水溶液除去金属氧化物。

公开(公告)号：US20050073051A1

公开(公告)日：2005-04-07

申请号：US10871282

申请日：2004-06-21

申请人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

发明人： Naoki Yamamoto ,  Akio Nishida ,  Akira Fujimoto ,  Hiraku Chakihara ,  Hideyuki Matsuoka ,  Toshiyuki Mine

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/02063 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L21/8221 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing process for a semiconductor integrated circuit device which prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The meal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

摘要翻译： 一种用于半导体集成电路器件的制造方法，其防止金属布线和硼掺杂硅插塞之间在其上形成的MOS晶体管的热处理中发生反应，并降低接触电阻上升的可能性。 金属硼化物形成在金属布线上的位于层间绝缘膜的开口底部的露出的金属表面上。 为了促进这种金属硼化物的形成，用氨水溶液除去残留在金属表面上的金属氧化物。 用高能量紫外线照射餐面，以除去残留在开口中的有机物质，并利用氨水溶液去除金属氧化物。

公开(公告)号：US20120211718A1

公开(公告)日：2012-08-23

申请号：US13440225

申请日：2012-04-05

申请人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： AKIO SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： H01L45/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US08125012B2

公开(公告)日：2012-02-28

申请号：US11639134

申请日：2006-12-15

申请人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

发明人： Toshiyuki Mine ,  Kan Yasui ,  Tetsuya Ishimaru ,  Yasuhiro Shimamoto

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L29/42344 ,  H01L29/512 ,  H01L29/513 ,  H01L29/792 ,  Y10S438/954

摘要： Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.

摘要翻译： 通过热电子进行电子写入和通过热孔进行空穴擦除的非易失性半导体存储装置的性能得到改善。 通过电子执行写入操作和通过空穴的擦除操作的非易失性存储单元具有设置在Si衬底上的p型阱区域，隔离区域，源极区域和漏极区域。 通过栅极绝缘膜在源极区域和漏极区域之间形成控制栅电极。 在控制栅电极的左侧壁形成有底部的氧化硅膜，电荷保持膜，顶部氧化物膜和存储栅电极。 电荷保持膜由化学计量过度地含有硅的氮化硅膜形成。

公开(公告)号：US07863134B2

公开(公告)日：2011-01-04

申请号：US12695271

申请日：2010-01-28

申请人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

发明人： Hirotaka Hamamura ,  Itaru Yanagi ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L29/4234 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/792

摘要： A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

摘要翻译： 存储单元中的电荷保持绝缘膜由半导体衬底上的底部绝缘膜，电荷存储膜和顶部绝缘膜构成的层叠膜构成。 此外，通过对底部绝缘膜进行等离子体氮化处理，在底部绝缘膜的上表面侧形成氮浓度为1原子％以上的氮化物区域。 将氮化物区域的厚度设定为0.5nm以上至1.5nm以下，将氮浓度的峰值设定为5原子％以上且40原子％以下，将氮的峰值的位置 浓度从底部绝缘膜的上表面设定在2nm以内，从而抑制底部绝缘膜与电荷存储膜之间的相互作用。

公开(公告)号：US07682990B2

公开(公告)日：2010-03-23

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed.For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20090134449A1

公开(公告)日：2009-05-28

申请号：US12273308

申请日：2008-11-18

申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

公开(公告)号：US20090085042A1

公开(公告)日：2009-04-02

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US07375399B2

公开(公告)日：2008-05-20

申请号：US11156558

申请日：2005-06-21

申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C2207/104 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

摘要翻译： 本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。 在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导 读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。 读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

公开(公告)号：US20080073705A1

公开(公告)日：2008-03-27

申请号：US11829248

申请日：2007-07-27

申请人： Digh HISAMOTO ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

发明人： Digh HISAMOTO ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.

摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。