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1.发明授权Magnetic nonvolatile memory cell and magnetic random access memory using the same 有权磁性非易失性存储单元和磁性随机存取存储器使用相同公开(公告)号：US07110284B2
公开(公告)日：2006-09-19
申请号：US10931041
申请日：2004-09-01
申请人： Jun Hayakawa , Hideyuki Matsuoka
发明人： Jun Hayakawa , Hideyuki Matsuoka
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetic nonvolatile memory cell includes a C-MOSFET, a spin torque magnetization inversion layer and a tunneling magnetoresistive layer arranged in this order. The memory cell has the function of spin torque magnetization inversion and consumes very low power. A random access memory includes a plurality of the memory cells.
摘要翻译： 磁性非易失性存储单元包括依次布置的C-MOSFET，自旋转矩磁化反转层和隧道磁阻层。 存储单元具有自旋转矩磁化反转的功能，并且消耗非常低的功率。 随机存取存储器包括多个存储单元。
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2.发明申请Magnetic nonvolatile memory cell and magnetic random access memory using the same 有权磁性非易失性存储单元和磁性随机存取存储器使用相同公开(公告)号：US20050117392A1
公开(公告)日：2005-06-02
申请号：US10931041
申请日：2004-09-01
申请人： Jun Hayakawa , Hideyuki Matsuoka
发明人： Jun Hayakawa , Hideyuki Matsuoka
IPC分类号： G11C11/15 , G11C11/14 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： G11C11/16
摘要： A magnetic nonvolatile memory cell includes a C-MOSFET, a spin torque magnetization inversion layer and a tunneling magnetoresistive layer arranged in this order. The memory cell has the function of spin torque magnetization inversion and consumes very low power. A random access memory includes a plurality of the memory cells.
摘要翻译： 磁性非易失性存储单元包括依次布置的C-MOSFET，自旋转矩磁化反转层和隧道磁阻层。 存储单元具有自旋转矩磁化反转的功能，并且消耗非常低的功率。 随机存取存储器包括多个存储单元。
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公开(公告)号：US20120241715A1
公开(公告)日：2012-09-27
申请号：US13493442
申请日：2012-06-11
申请人： YUICHI MATSUI , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： YUICHI MATSUI , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
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公开(公告)号：US20090250680A1
公开(公告)日：2009-10-08
申请号：US12487492
申请日：2009-06-18
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译： 通过高速非易失性相变存储器，提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。 结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。
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公开(公告)号：US07372726B2
公开(公告)日：2008-05-13
申请号：US11547616
申请日：2005-04-01
IPC分类号： G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.
摘要翻译： 公开了一种使用硫属化物作为记录介质的相变存储器，其防止产生读取干扰并高速读取数据。 在包括选择晶体管和硫族化物的相变存储单元阵列中，选择晶体管的衬底电位在垂直于字线的方向上被隔离。 在数据记录期间，正向电流信号在衬底和连接到硫族化物的源极线之间流动，并且不使用选择晶体管。 在数据读取期间，选择晶体管选择所需的单元。 因此，记录电压大大高于读取电压，从而防止读取干扰的发生，并且实现高速操作。
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公开(公告)号：US07335907B2
公开(公告)日：2008-02-26
申请号：US10790881
申请日：2004-03-03
IPC分类号： H01L47/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1213 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： A phase change memory device is provided which is constituted by memory cells using memory elements and select transistors and having high heat resistance to be capable of an operation at 140 degrees or higher. As a device configuration, a recording layer of which, of Zn—Ge—Te, content of Zn, Cd or the like is 20 atom percent or more, content of at least one element selected from the group consisting of Ge and Sb is less than 40 atom percent, and content of Te is 40 atom percent or more is used. It is thereby possible to implement the memory device usable for an application which may be performed at a high temperature such as an in-vehicle use.
摘要翻译： 提供一种相变存储器件，其由使用存储元件和选择晶体管的存储器单元构成，并且具有高耐热性能够在140度以上的操作。 作为器件结构，其中Zn-Ge-Te，Zn，Cd等的含量为20原子％以上的记录层选自Ge和Sb中的至少一种元素的含量较少 40原子％以上，Te含量为40原子％以上。 由此，可以实现可以在诸如车载用途的高温下执行的应用的存储装置。
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公开(公告)号：US20070217254A1
公开(公告)日：2007-09-20
申请号：US11547616
申请日：2005-04-01
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.
摘要翻译： 公开了一种使用硫属化物作为记录介质的相变存储器，其防止产生读取干扰并高速读取数据。 在包括选择晶体管和硫族化物的相变存储单元阵列中，选择晶体管的衬底电位在垂直于字线的方向上被隔离。 在数据记录期间，正向电流信号在衬底和连接到硫族化物的源极线之间流动，并且不使用选择晶体管。 在数据读取期间，选择晶体管选择所需的单元。 因此，记录电压大大高于读取电压，从而防止读取干扰的发生，并且实现高速操作。
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8.发明申请Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device 审中-公开垂直错位制造方法，垂直错位，半导体存储器件制造方法和半导体存储器件公开(公告)号：US20070202638A1
公开(公告)日：2007-08-30
申请号：US11790130
申请日：2007-04-24
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/84
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译： 半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。 在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼 来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。
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公开(公告)号：US20070170413A1
公开(公告)日：2007-07-26
申请号：US11596220
申请日：2005-05-09
申请人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。
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10.发明授权Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film 失效具有冠状电容器布置的半导体存储器布置在层间绝缘膜中沟槽公开(公告)号：US07196368B2
公开(公告)日：2007-03-27
申请号：US10914223
申请日：2004-08-10
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线， 选择线。 由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触， 外围电路区域和存储单元区域之间的台阶高度显着降低。
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