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471 条记录 (耗时 0.055 秒)

    Method and apparatus for operating a cache memory in a multi-processor
    91.
    发明授权
    Method and apparatus for operating a cache memory in a multi-processor 失效
    用于在多处理器中操作高速缓冲存储器的方法和装置

    公开(公告)号：US5113510A

    公开(公告)日：1992-05-12

    申请号：US136580

    申请日：1987-12-22

    申请人： W. Daniel Hillis

    发明人： W. Daniel Hillis

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0833

    摘要： A computer system having a plurality of processors with each processor having associated therewith a cache memory is disclosed. When it becomes necessary for a processor to update its cache with a block of data from main memory, such a block of data is simultaneously loaded into each appropriate cache. Thus, each processor subsequently requiring such updated block of data may retrieve the block from its own cache, and not be required to access main memory.

    摘要翻译： 公开了具有多个处理器的计算机系统，每个处理器具有与其相关联的高速缓冲存储器。 当处理器需要用来自主存储器的数据块更新其高速缓存时，这样的数据块被同时加载到每个适当的高速缓存中。 因此，随后要求这种更新的数据块的每个处理器可以从其自己的高速缓存中检索该块，而不需要访问主存储器。

    Puzzles comprised of elements each having a unique arrangement of matchable features
    92.
    发明授权
    Puzzles comprised of elements each having a unique arrangement of matchable features 失效
    由各自具有独特布置的匹配特征的元件组成的拼图

    公开(公告)号：US4830376A

    公开(公告)日：1989-05-16

    申请号：US142047

    申请日：1988-01-07

    申请人： W. Daniel Hillis

    发明人： W. Daniel Hillis

    IPC分类号： A63F9/10 ,  A63F9/12

    CPC分类号： A63F9/12 ,  A63F9/10

    摘要： A two dimensional puzzle is disclosed comprising thirty-six four sided tiles. Each of the tiles includes some means for indicating its orientation; and all but one of the tiles further comprises a part of at least one means for matching the tile to other tiles. The matching means illustratively is an interlocking connector having a male and female element one of which elements is disposed in a side of a first tile and the other of which is disposed in a side of a second tile to which the first tile is connected. Each of the four side surfaces of each tile has either a male connector element, a female connector element or neither element; and each tile has a different combination of these three features on its four sides. The puzzle is to arrange the thirty-six tiles in their correct orientation in a six-by-six rectilinear array so that the tiles interlock. Extensions of the puzzle to other dimensions are also disclosed, in particular, a three-dimensional puzzle of 216 blocks that can be assembled in a six-by-six-by-six array of interlocking blocks.

    摘要翻译： 公开了一种二维拼图，其包括三十六个四面砖。 每个瓦片包括一些用于指示其方向的装置; 并且除了一个瓷砖之外的所有瓷砖还包括至少一个用于将砖与其他砖相匹配的装置的一部分。 匹配装置示例性地是具有阳和阴元件的互锁连接器，其中一个元件设置在第一瓦片的侧面，另一个元件设置在第一瓦片连接到第二瓦片的一侧。 每个瓦片的四个侧表面中的每一个具有阳连接器元件，阴连接器元件或两个元件; 并且每个瓦片在其四面具有这三个特征的不同组合。 拼图是将六十六个瓷砖以正六六位直线阵列排列成正确的方式，以使瓷砖互相联锁。 还公开了其他尺寸的拼图的扩展，特别是216个块的三维拼图，其可以以六乘六乘六排的互锁块组装。

    Parallel processor/memory circuit
    93.
    发明授权
    Parallel processor/memory circuit 失效
    并行处理器/存储器电路

    公开(公告)号：US4709327A

    公开(公告)日：1987-11-24

    申请号：US499471

    申请日：1983-05-31

    申请人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

    发明人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

    IPC分类号： G06F15/80 ,  G06F15/16

    CPC分类号： G06F15/8023

    摘要： A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith.Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.

    摘要翻译： 公开了一种用于高度并行处理器中的处理器/存储器的并行处理电路。 电路包括指令解码器，其响应于在解码器处接收到的指令而生成输出表，以及多个处理器/存储器，每个处理器/存储器包括读/写存储器和用于至少部分地基于数据读取产生输出的处理器 从在指令解码器处接收的存储器和指令信息。 此外，电路提供用于同时寻址每个读/写存储器中的至少一个单元以向其中写入数据或从其读取数据的装置，用于向每个处理器提供来自解码器的输出表的装置，该特定输出表取决于指令信息 在解码器处接收。 此外，处理电路包括用于根据输入到处理器的数据从输出表选择特定输出的装置。 有利地，每个处理器/存储器还包括用于控制多个标志的读取的标志控制器和用于同时寻址每个标志控制器以读取用于输入到与其相关联的处理器的标志的装置。 优选地，每个处理器是具有三个输入的位串行处理器，两个来自读/写存储器和一个来自标志控制器的两个输出，一个输出到读/写存储器，一个输出到该标志控制器; 以及解码器和多个处理器/存储器并形成在单个集成电路芯片上。

    Data store with lock-free stateless paging capability
    95.
    发明授权
    Data store with lock-free stateless paging capability 有权
    数据存储，无锁无状态寻呼功能

    公开(公告)号：US08996486B2

    公开(公告)日：2015-03-31

    申请号：US11301985

    申请日：2005-12-12

    申请人： W. Daniel Hillis ,  Eric Bax ,  Augusto Callejas ,  Harry Kao ,  Mathias L. Kolehmainen

    发明人： W. Daniel Hillis ,  Eric Bax ,  Augusto Callejas ,  Harry Kao ,  Mathias L. Kolehmainen

    IPC分类号： G06F7/00 ,  G06F17/30

    CPC分类号： G06F17/30867 ,  G06F17/3053 ,  G06F17/30545 ,  G06F17/30592 ,  G06F17/30876

    摘要： Disclosed are a method and apparatus for limiting the number of results returned by a data store in response to a query. Upon receiving an initial query, the data store returns a page of results that includes a subset of the data items within the data store satisfying the conditions of the query. The data store also provides a marker indicating the extent of the set of data items. If a subsequent query that requests additional results which satisfy the same query conditions and that includes the marker is received, the data store returns a page of results that includes a subset of data items that are disjoint from the initial subset, and provides an updated marker which indicates the extent of the union of the initial and subsequent subsets. If still further results are desired from the data store, an additional query containing the updated marker may be submitted.

    摘要翻译： 公开了一种用于限制响应于查询的数据存储返回的结果的数量的方法和装置。 在接收到初始查询之后，数据存储返回包含符合查询条件的数据存储库内数据项子集的结果页。 数据存储还提供指示数据项集的范围的标记。 如果接收到请求满足相同查询条件并且包括标记的附加结果的后续查询，则数据存储返回包括与初始子集不相交的数据项的子集的结果页面，并提供更新的标记 这表明初始和后续子集的联合程度。 如果从数据存储还需要进一步的结果，则可以提交包含更新的标记的附加查询。