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公开(公告)号:US10170381B2
公开(公告)日:2019-01-01
申请号:US15704246
申请日:2017-09-14
发明人: Michael J. Seddon , Heng Chen Lee
摘要: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
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公开(公告)号:US10115716B2
公开(公告)日:2018-10-30
申请号:US14812846
申请日:2015-07-29
IPC分类号: H01L25/00 , H01L21/48 , H01L23/00 , H01L23/495 , H01L23/498 , H01L25/065 , H01L23/482
摘要: A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The alloy has a melting temperature higher than the first reflow temperature. Accordingly, additional die may be added at a later time and reflowed to attach to the board without causing the bonding of the first die to the board to fail.
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公开(公告)号:US10109475B2
公开(公告)日:2018-10-23
申请号:US15223405
申请日:2016-07-29
发明人: Michael J. Seddon
IPC分类号: H01L21/30 , H01L21/02 , H01L21/683 , H01L21/78 , H01L23/544 , H01L23/00 , H01L21/304
摘要: A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
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94.
公开(公告)号:US10096460B2
公开(公告)日:2018-10-09
申请号:US15226362
申请日:2016-08-02
发明人: Michael J. Seddon
IPC分类号: B24B7/22 , H01L21/02 , H01L21/67 , H01L23/544 , H01L21/78 , H01L21/768 , H01L21/66 , B24B55/06
摘要: A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.
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公开(公告)号:US20150228494A1
公开(公告)日:2015-08-13
申请号:US14690972
申请日:2015-04-20
IPC分类号: H01L21/304 , H01L21/3065 , H01L21/78
CPC分类号: H01L21/02076 , H01L21/3043 , H01L21/3046 , H01L21/3065 , H01L21/67028 , H01L21/6836 , H01L21/78 , H01L21/7813 , H01L23/544 , H01L2221/68327 , H01L2223/5446
摘要: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.
摘要翻译: 在一个实施例中,通过将半导体晶片放置在载体带上,背衬层与载带相邻,将半导体晶片从具有背金属层的半导体晶片分离,通过半导体晶片形成分割线,以暴露分离线内的后金属层 并且使用流体分离后金属层的部分。
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公开(公告)号:US12132008B2
公开(公告)日:2024-10-29
申请号:US17813357
申请日:2022-07-19
IPC分类号: H01L23/00 , H01L23/31 , H01L23/32 , H01L25/065
CPC分类号: H01L23/562 , H01L23/31 , H01L23/32 , H01L25/0655
摘要: Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.
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公开(公告)号:US12132005B2
公开(公告)日:2024-10-29
申请号:US18507176
申请日:2023-11-13
IPC分类号: H01L23/544 , H01L23/14 , H01L23/32 , H01L25/065
CPC分类号: H01L23/544 , H01L23/145 , H01L23/32 , H01L25/0655
摘要: Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
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公开(公告)号:US11987874B2
公开(公告)日:2024-05-21
申请号:US16254904
申请日:2019-01-23
发明人: Michael J. Seddon
CPC分类号: C23C14/18 , C23C14/243 , C23C14/5873
摘要: Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.
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公开(公告)号:US11854889B2
公开(公告)日:2023-12-26
申请号:US16929542
申请日:2020-07-15
发明人: Michael J. Seddon
IPC分类号: H01L21/78 , H01L21/268 , H01L21/02 , H01L21/304 , H01L21/683 , H01L23/544 , B23K26/53 , B23K26/00 , B23K101/40
CPC分类号: H01L21/78 , H01L21/02076 , H01L21/268 , H01L21/3043 , H01L21/6836 , H01L23/544 , B23K26/0006 , B23K26/53 , B23K2101/40 , H01L2223/5446
摘要: Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.
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公开(公告)号:US11830756B2
公开(公告)日:2023-11-28
申请号:US16862063
申请日:2020-04-29
IPC分类号: B32B43/00 , H01L21/683
CPC分类号: H01L21/6835 , B32B43/006 , B32B2307/732 , H01L2221/6834 , H01L2221/68354 , H01L2221/68386
摘要: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.
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