公开(公告)号：US08994887B2

公开(公告)日：2015-03-31

申请号：US14499313

申请日：2014-09-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado

IPC: G02F1/136 ,  G02F1/1343 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1362

CPC classification number: H01L27/1255 ,  G02F1/13454 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136286 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78645 ,  H01L29/78651 ,  H01L29/78675

Abstract: In an active matrix type liquid crystal display device, in which functional circuits such as a shift register circuit and a buffer circuit are incorporated on the same substrate, an optimal TFT structure is provided along with the aperture ratio of a pixel matrix circuit is increased. There is a structure in which an n-channel TFT, with a third impurity region which overlaps a gate electrode, is formed in a buffer circuit, etc., and an n-channel TFT, in which a fourth impurity region which does not overlap the gate electrode, is formed in a pixel matrix circuit. A storage capacitor formed in the pixel matrix circuit is formed by a light shielding film, a dielectric film formed on the light shielding film, and a pixel electrode. Al is especially used in the light shielding film, and the dielectric film is formed anodic oxidation process, using an Al oxide film.

Abstract translation: 在有源矩阵型液晶显示装置中，其中诸如移位寄存器电路和缓冲电路的功能电路并入同一衬底上，提供了最佳的TFT结构，同时增加了像素矩阵电路的孔径比。 存在这样的结构，其中在缓冲电路等中形成具有与栅电极重叠的第三杂质区的n沟道TFT，以及n沟道TFT，其中不重叠的第四杂质区 栅电极形成在像素矩阵电路中。 形成在像素矩阵电路中的保持电容器由遮光膜，形成在遮光膜上的电介质膜和像素电极形成。 Al特别用于遮光膜，并且使用Al氧化物膜形成电介质膜的阳极氧化工艺。

公开(公告)号：US08975930B2

公开(公告)日：2015-03-10

申请号：US13961066

申请日：2013-08-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama

IPC: H03B1/00 ,  H01L27/06 ,  H03K3/012 ,  H01L27/12 ,  H03K19/00 ,  H01L27/092 ,  H01L29/786

CPC classification number: H03K3/012 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/78648 ,  H03K19/0013

Abstract: Direct-path current is reduced in a semiconductor device including CMOS circuits. One embodiment of the present invention is a method for driving a semiconductor device that includes a first CMOS circuit between power supply lines, a first transistor between the power supply lines, a second CMOS circuit between the power supply lines, and a second transistor between an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit. The first transistor and the second transistor each have lower off-state current than a transistor included in the first CMOS circuit. In a period during which the voltage of a first signal input to the first CMOS circuit is changed, a second signal is input to the first transistor and the second transistor to turn off the first transistor and the second transistor.

Abstract translation: 在包括CMOS电路的半导体器件中，直通电流减小。 本发明的一个实施例是一种用于驱动半导体器件的方法，该半导体器件包括电源线之间的第一CMOS电路，电源线之间的第一晶体管，电源线之间的第二CMOS电路和位于电源线之间的第二晶体管 第一CMOS电路的输出端子和第二CMOS电路的输入端子。 第一晶体管和第二晶体管分别具有比包含在第一CMOS电路中的晶体管更低的截止电流。 在其中输入到第一CMOS电路的第一信号的电压改变的时段中，第二信号被输入到第一晶体管和第二晶体管，以关断第一晶体管和第二晶体管。

公开(公告)号：US20150035514A1

公开(公告)日：2015-02-05

申请号：US14445370

申请日：2014-07-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun Koyama ,  Kei Takahashi

IPC: H01L27/12 ,  H01L29/786 ,  H02M3/158

CPC classification number: H02M3/156 ,  G09G3/2092 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696 ,  H02M3/33523 ,  H02M3/33553 ,  H03K7/08

Abstract: A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

Abstract translation: 提供具有低功耗和高功率转换效率的DC-DC转换器。 DC-DC转换器包括第一晶体管和控制电路。 控制电路包括运算放大器，其产生控制第一晶体管的切换的信号，产生施加到运算放大器的偏置电位的偏置电路和保持偏置电位的保持电路。 保持电路包括第二晶体管和提供偏置电位的电容器。 第一晶体管和第二晶体管分别包括第一氧化物半导体膜和第二氧化物半导体膜。 第一氧化物半导体膜和第二氧化物半导体膜各自含有In，M（M为Ga，Y，Zr，La，Ce或Nd）和Zn。 第一氧化物半导体膜中的In与M的原子比高于第二氧化物半导体膜中的原子比。

公开(公告)号：US20150035033A1

公开(公告)日：2015-02-05

申请号：US14322990

申请日：2014-07-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

IPC: H01L27/32 ,  H01L27/12

CPC classification number: H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

Abstract translation: 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。

公开(公告)号：US20150034922A1

公开(公告)日：2015-02-05

申请号：US14330074

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama

IPC: H01L27/32

CPC classification number: G09G3/3208 ,  C09K11/06 ,  C09K2211/1088 ,  C09K2211/185 ,  G09G3/2022 ,  G09G3/3241 ,  G09G3/3266 ,  G09G3/3283 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/027 ,  G09G2320/0247 ,  G09G2320/0266 ,  G09G2320/041 ,  H01L27/1222 ,  H01L27/1285 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3279 ,  H01L51/0096 ,  H01L51/5259 ,  H01L2251/301 ,  H05B33/14

Abstract: The present invention is to provide a light emitting device capable of obtaining a certain luminance without influence by the temperature change, and a driving method thereof. A current mirror circuit formed by using a transistor is provided for each pixel. The first transistor and the second transistor of the current mirror circuit are connected such that the drain currents thereof are maintained at proportional values regardless of the load resistance value. Thereby, a light emitting device capable of controlling the OLED driving current and the luminance of the OLED by controlling the drain current of the first transistor at a value corresponding to a video signal in a driving circuit, and supplying the drain current of the second transistor to the OLED, is provided.

公开(公告)号：US20150016585A1

公开(公告)日：2015-01-15

申请号：US14315601

申请日：2014-06-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kouhei Toyotaka ,  Jun Koyama ,  Hiroyuki Miyake

IPC: G09G3/36 ,  G11C19/28 ,  H03K3/012 ,  H03K17/687

CPC classification number: H01L27/124 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0626 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Abstract translation: 半导体器件包括具有相同导电类型的第一和第二晶体管和电路。 第一晶体管的源极和漏极之一与第二晶体管的源极和漏极电连接。 第一和第三电位通过各自的布线提供给电路。 第二电位和第一时钟信号分别被提供给第一和第二晶体管的源极和漏极中的其它电极。 第二个时钟信号被提供给电路。 第三电位高于高于第一电位的第二电位。 第四个电位等于或高于第三个电位。 第一时钟信号交替第二和第四电位，第二时钟信号交替第一和第三电位。 该电路控制第一和第二晶体管的栅极与布线之间的电连接。

公开(公告)号：US20150001544A1

公开(公告)日：2015-01-01

申请号：US14321874

申请日：2014-07-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Keisuke Miyagawa ,  Jun Koyama

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2320/029 ,  G09G2320/0295 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2330/028

Abstract: A conventional setting voltage was a value with an estimated margin of a characteristic change of a light emitting element. Therefore, a voltage between the source and drain of a driver transistor Vds had to be set high (Vds≧Vgs−VTh+a). This caused high heat generation and power consumption because a voltage applied to the light emitting element. The invention is characterized by feedbacking a change in a current value in accordance with the deterioration of a light emitting element and a power source voltage controller which modifies a setting voltage. Namely, according to the invention, the setting voltage is to be set in the vicinity of the boundary (critical part) between a saturation region and a linear region, and a voltage margin for the deterioration is not required particularly for an initial setting voltage.

Abstract translation: 传统的设定电压是具有发光元件的特性变化的估计裕量的值。 因此，必须将驱动晶体管Vds的源极和漏极之间的电压设置为高（Vds≥Vgs-VTh + a）。 这导致由于施加到发光元件的电压而导致高的发热和功率消耗。 本发明的特征在于根据改变设定电压的发光元件和电源电压控制器的劣化反馈电流值的变化。 也就是说，根据本发明，将设定电压设定在饱和区域和线性区域之间的边界（临界部分）附近，并且对初始设定电压不需要劣化的电压余量。

公开(公告)号：US08922537B2

公开(公告)日：2014-12-30

申请号：US14089025

申请日：2013-11-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Hiroyuki Miyake

IPC: G09G5/00 ,  G09G3/36 ,  G02F1/1345

CPC classification number: G09G3/3618 ,  G02F1/1345 ,  G06F3/0416 ,  G06F3/0421 ,  G06F3/044 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3696 ,  G09G2300/0809 ,  G09G2310/04 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2320/10 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2340/16 ,  G09G2354/00

Abstract: The liquid crystal display device includes a first substrate provided with a terminal portion, a switching transistor, a driver circuit portion, and a pixel circuit portion including a pixel transistor and a plurality of pixels, a second substrate provided with a common electrode electrically connected to the terminal portion through the switching transistor, and liquid crystal between a pixel electrode and the common electrode. In a period during which a still image is switched to a moving image, the following steps are sequentially performed: a first step of supplying the common potential to the common electrode; a second step of supplying a power supply voltage to the driver circuit portion; a third step of supplying a clock signal to the driver circuit portion; and a fourth step of supplying a start pulse signal to the driver circuit portion.

Abstract translation: 液晶显示装置包括具有端子部分的第一基板，开关晶体管，驱动电路部分和包括像素晶体管和多个像素的像素电路部分，第二基板设置有电连接到 通过开关晶体管的端子部分和像素电极与公共电极之间的液晶。 在将静止图像切换为运动图像的期间中，依次执行以下步骤：将公共电位提供给公共电极的第一步骤; 向驱动电路部供给电源电压的第2工序; 向所述驱动电路部提供时钟信号的第三步骤; 以及向所述驱动器电路部分提供起始脉冲信号的第四步骤。

公开(公告)号：US20140367679A1

公开(公告)日：2014-12-18

申请号：US14472605

申请日：2014-08-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/45 ,  H01L29/78645 ,  H03K17/0822

Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.

Abstract translation: 该半导体器件包括：功率元件，其在不向栅极施加电压时处于导通状态，用于向功率元件的栅极施加第一电压的开关场效应晶体管，以及用于施加电压的开关场效应晶体管 低于功率元件的栅极的第一电压。 开关场效应晶体管具有小的截止电流。

公开(公告)号：US20140340365A1

公开(公告)日：2014-11-20

申请号：US14449864

申请日：2014-08-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Takayuki IKEDA

IPC: G06F3/041 ,  G06F3/042

CPC classification number: G06F3/0416 ,  G06F3/0412 ,  G06F3/042 ,  G09G3/20 ,  G09G3/3666 ,  G09G3/3688 ,  G09G2310/0221 ,  G09G2310/0248 ,  G09G2320/0626 ,  G09G2360/144

Abstract: To increase a reading speed in a display device having a touch-panel function. The display device includes a display panel 101 and a controller substrate 115. The display panel 101 includes a pixel portion 102, source drivers 103, 104, 105, 106, 107, 108, 109, and 110, display gate drivers 111 and 112, and reading gate drivers 113 and 114. The controller substrate 115 includes a controller IC 116. The controller substrate 115 is electrically connected to the display panel 101 through a connecting FPC 117.

Abstract translation: 为了提高具有触摸面板功能的显示装置的读取速度。 显示装置包括显示面板101和控制器基板115.显示面板101包括像素部分102，源极驱动器103,104,105,106,107,108,109和110，显示栅极驱动器111和112， 和读取门驱动器113和114.控制器基板115包括控制器IC 116.控制器基板115通过连接FPC 117电连接到显示面板101。