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    Resonant cavity complementary optoelectronic transistors
    92.
    发明授权
    Resonant cavity complementary optoelectronic transistors 有权
    谐振腔互补光电晶体管

    公开(公告)号：US08084795B2

    公开(公告)日：2011-12-27

    申请号：US12470566

    申请日：2009-05-22

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01S5/00 ,  H01L33/00

    CPC classification number: H01S5/0261 ,  H01L27/15 ,  H01S5/0262

    Abstract: The CMOS field effect transistors, used in microprocessors and other digital VLSI circuits, face major challenges such as thin gate dielectrics leakage and scaling limits, severe short channel effects, limited performance improvement with scaling, complicated fabrication process with added special techniques, and surface mobility degradation. This disclosure proposes a new CMOS-compatible optoelectronic transistor. The current is much higher than the MOS transistors, due to the high carrier mobility with bulk transportation. The optoelectronic transistors are scalable to the sub-nanometer ranges without short channel effects. It is also suitable for low power applications and ULSI circuits. The new transistor consists of a laser or LED diode as drain or source, and a photo sensor diode (avalanche photo diode) as source or drain. The transistor is turned on by applying a gate voltage, similar to the CMOS transistors, and a laser or LED light signal is sent to the nearby photo diode, causing an avalanche breakdown and high drain current. The transistor is surrounded by dielectrics and metal isolations, which serve as a metal box or cavity, so the generated laser or LED lights are confined and reflected back from the metal. The drain current increases exponentially with the drain or gate voltage. This exponential drain current vs. drain or gate voltage characteristics makes the optoelectronic transistor run much faster than the transitional linear MOSFET.The optic transistor current-voltage characteristics are totally different from transitional CMOS transistors.

    Abstract translation: 在微处理器和其他数字VLSI电路中使用的CMOS场效应晶体管面临诸如薄栅极电介质泄漏和结垢限制，严重的短沟道效应，缩放的有限性能改进，附加特殊技术的复杂制造工艺和表面迁移率等主要挑战 降解。 本公开提出了一种新的兼容CMOS的光电晶体管。 电流远高于MOS晶体管，这是由于大容量运输的高载流子迁移率。 光电子晶体管可以扩展到亚纳米范围，而没有短信道效应。 它也适用于低功率应用和ULSI电路。 新的晶体管由激光器或LED二极管作为漏极或源极，以及作为源极或漏极的光电二极管（雪崩光电二极管）组成。 通过施加类似于CMOS晶体管的栅极电压来接通晶体管，并且将激光或LED光信号发送到附近的光电二极管，导致雪崩击穿和高漏极电流。 晶体管被电介质和金属隔离物所围绕，它们用作金属盒或空腔，因此产生的激光或LED灯被限制并从金属反射回来。 漏极电流随漏极或栅极电压呈指数增长。 该指数漏极电流与漏极或栅极电压特性使得光电晶体管的运行比过渡线性MOSFET快得多。 光晶体管电流 - 电压特性与过渡CMOS晶体管完全不同。

    Replacement metal gate transistors with reduced gate oxide leakage
    93.
    发明授权
    Replacement metal gate transistors with reduced gate oxide leakage 有权
    替代金属栅极晶体管，栅极氧化物泄漏减少

    公开(公告)号：US08053849B2

    公开(公告)日：2011-11-08

    申请号：US11269745

    申请日：2005-11-09

    Applicant: James Pan ,  John Pellerin

    Inventor： James Pan ,  John Pellerin

    IPC: H01L21/02

    CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/28238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.

    Abstract translation: 通过在栅极氧化层和金属栅电极之间形成保护层来实现用于替换金属栅极晶体管的具有减小的泄漏的薄的有效栅极氧化物厚度，从而降低应力。 实施例包括形成从金属栅电极朝向保护层的栅极氧化物层浓缩的含有金属碳化物的非晶碳保护层。 方法的实施例包括去除可移除栅极，在栅极氧化物层上沉积无定形碳层，形成金属栅电极，然后在升高的温度下加热以使金属从金属栅电极扩散到无定形碳层中，从而形成 金属碳化物。 实施例还包括具有高介电常数的栅极氧化物层和在与金属栅电极和衬底的界面处集中的硅的金属栅极晶体管。

    STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES
    94.
    发明申请
    STRUCTURE AND METHOD FOR SEMICONDUCTOR POWER DEVICES 有权
    半导体功率器件的结构与方法

    公开(公告)号：US20110133275A1

    公开(公告)日：2011-06-09

    申请号：US13028054

    申请日：2011-02-15

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L27/06

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/78624

    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

    Abstract translation: 半导体器件包括在衬底上的绝缘体上半导体区域。 绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。 该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。 该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。 双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。 因此，MOS晶体管的漏极也用作双极晶体管的发射极。 此外，栅极和基极通过电阻元件耦合。

    Structure and method for semiconductor power devices
    95.
    发明授权
    Structure and method for semiconductor power devices 有权
    半导体功率器件的结构和方法

    公开(公告)号：US07910995B2

    公开(公告)日：2011-03-22

    申请号：US12109293

    申请日：2008-04-24

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/78624

    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

    Abstract translation: 半导体器件包括在衬底上的绝缘体上半导体区域。 绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。 该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。 该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。 双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。 因此，MOS晶体管的漏极也用作双极晶体管的发射极。 此外，栅极和基极通过电阻元件耦合。

    High density trench field effect transistor
    97.
    发明申请
    High density trench field effect transistor 有权
    高密度沟槽场效应晶体管

    公开(公告)号：US20100065904A1

    公开(公告)日：2010-03-18

    申请号：US12211654

    申请日：2008-09-16

    Applicant: James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

    Inventor： James Pan ,  Scott L. Hunt ,  Dean E. Probst ,  Hossein Paravi

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7397

    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

    Abstract translation: 半导体结构包括延伸到半导体区域中的沟槽。 半导体区域的部分在形成台面区域的相邻沟槽之间延伸。 栅电极在每个沟槽中。 第一导电类型的阱区在相邻沟槽之间的半导体区域中延伸。 第二导电类型的源极区位于阱区中。 第一导电类型的重体区域在井区域中。 源极区域和重体区域是相邻的沟槽侧壁，并且重体区域沿着沟槽侧壁延伸到源区域上方到台面区域的顶表面。

    Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings
    99.
    发明申请
    Structure and Method for Forming Power Devices with High Aspect Ratio Contact Openings 有权
    用于形成具有高纵横比接触开口的功率器件的结构和方法

    公开(公告)号：US20090189218A1

    公开(公告)日：2009-07-30

    申请号：US12333597

    申请日：2008-12-12

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings.

    Abstract translation: 场效应晶体管（FET）包括在第二导电类型的半导体区域上的第一导电类型的体区。 第二导电类型的源区域在身体区域上延伸。 栅电极通过栅极介电层相邻延伸而与体区绝缘。 接触开口延伸到相邻栅电极之间的主体区域。 种子层沿着每个接触开口的底部延伸。 种子层用作促进导电填充材料生长的成核位点。 导电填充材料填充每个接触开口的下部。 互连层填充每个接触开口的上部并与导电填充材料直接接触。 互连层也沿着接触开口的上侧壁的相应源极区直接接触。

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