公开(公告)号：US20150108470A1

公开(公告)日：2015-04-23

申请号：US14515993

申请日：2014-10-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidekazu Miyairi

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor, A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

Abstract translation: 提供适合于小型化的半导体器件。 半导体器件包括第一晶体管，第一晶体管上的第二晶体管，第一晶体管和第二晶体管之间的阻挡层，第一晶体管和阻挡层之间的第一电极，以及位于毛发层与第二晶体管之间的第二电极 第二晶体管并且与第一电极重叠，其间具有阻挡层。 第一晶体管的栅电极，第一电极，第二晶体管的源电极和漏极之一彼此电连接。 在第一晶体管中的包括单晶半导体的第一半导体层中形成沟道，在第二晶体管中的包含氧化物半导体的第二半导体层中形成沟道。

公开(公告)号：US20140269099A1

公开(公告)日：2014-09-18

申请号：US14200430

申请日：2014-03-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US20140264521A1

公开(公告)日：2014-09-18

申请号：US14287285

申请日：2014-05-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: H01L27/105

CPC classification number: H01L27/1052 ,  G11C8/08 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4085 ,  G11C16/02 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/4016

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract translation: 即使在不提供电力的情况下也可以保存存储的数据，并且没有限制写入操作的数量的半导体装置。 使用可以充分降低诸如作为宽间隙半导体的氧化物半导体材料的晶体管的截止电流的材料形成半导体器件。 当使用可以充分降低晶体管的截止电流的半导体材料时，半导体器件可以长期保存数据。 此外，通过提供电连接到写字线的电容器或噪声去除电路，可以减少或去除诸如短脉冲或输入到存储器单元的噪声的信号。 因此，可以防止当存储单元中的晶体管瞬间导通时擦除写入存储单元的数据的故障。

公开(公告)号：US08837232B2

公开(公告)日：2014-09-16

申请号：US13940493

申请日：2013-07-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/403 ,  G11C11/4087 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Abstract translation: 目的是提供具有新颖结构的半导体器件，其即使在不提供电力且具有无限数量的写周期的情况下也可以保存存储的数据。 使用包括诸如氧化物半导体的宽带隙半导体的存储单元形成半导体器件。 半导体器件包括具有输出低于用于从存储单元读取数据的参考电位的电位的功能的电位变化电路。 当使用允许充分降低包含在存储单元中的晶体管的截止电流的宽带隙半导体时，可以提供能够长期保存数据的半导体器件。

公开(公告)号：US08711623B2

公开(公告)日：2014-04-29

申请号：US13848871

申请日：2013-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Toshihiko Saito ,  Shuhei Nagatsuka

IPC: G11C14/00 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00 ,  G11C16/0433

Abstract: One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.

Abstract translation: 其目的之一是提供一种非易失性存储器件，其中数据写入中的缺陷的发生被抑制并且其面积可被抑制，或者包括非易失性存储器件的半导体器件。 提供了一种包括非易失性存储元件和用于临时存储数据的第二存储器部分（数据缓冲器）的第一存储器部分，其被验证是否将数据正确写入第一存储器部分的验证操作。 此外，第二存储器部分包括用于控制存储元件中的电荷的保持的存储元件和绝缘栅场效应晶体管; 晶体管的截止电流或漏电流极低。

公开(公告)号：US20130341615A1

公开(公告)日：2013-12-26

申请号：US13913591

申请日：2013-06-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

IPC: H01L27/088

CPC classification number: H01L27/088 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225

Abstract: A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(∈ra/∈rb)

Abstract translation: 具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。 第一晶体管和第二晶体管被设置为至少部分地彼此重叠。 第二晶体管的绝缘层和栅绝缘层满足下式：（ta / tb）×（Era / Erb）<0.1，其中ta表示栅绝缘层的厚度，tb表示绝缘层的厚度 时，代表栅极绝缘层的介电常数，Erb表示绝缘层的介电常数。

公开(公告)号：US20130301367A1

公开(公告)日：2013-11-14

申请号：US13940493

申请日：2013-07-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Kiyoshi Kato

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/403 ,  G11C11/4087 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure, which can hold stored data even when power is not supplied and which has an unlimited number of write cycles. The semiconductor device is formed using a memory cell including a wide band gap semiconductor such as an oxide semiconductor. The semiconductor device includes a potential change circuit having a function of outputting a potential lower than a reference potential for reading data from the memory cell. When the wide band gap semiconductor which allows a sufficient reduction in off-state current of a transistor included in the memory cell is used, a semiconductor device which can hold data for a long period can be provided.

Abstract translation: 目的是提供具有新颖结构的半导体器件，其即使在不提供电力且具有无限数量的写周期的情况下也可以保存存储的数据。 使用包括诸如氧化物半导体的宽带隙半导体的存储单元形成半导体器件。 半导体器件包括具有输出低于用于从存储单元读取数据的参考电位的电位的功能的电位变化电路。 当使用允许充分降低包含在存储单元中的晶体管的截止电流的宽带隙半导体时，可以提供能够长期保存数据的半导体器件。

公开(公告)号：US20130223157A1

公开(公告)日：2013-08-29

申请号：US13848871

申请日：2013-03-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito ,  Shuhei Nagatsuka

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00 ,  G11C16/0433

Abstract: One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.

Abstract translation: 其目的之一是提供一种非易失性存储器件，其中数据写入中的缺陷的发生被抑制并且其面积可被抑制，或者包括非易失性存储器件的半导体器件。 提供了一种包括非易失性存储元件和用于临时存储数据的第二存储器部分（数据缓冲器）的第一存储器部分，其被验证是否将数据正确写入第一存储器部分的验证操作。 此外，第二存储器部分包括用于控制存储元件中的电荷的保持的存储元件和绝缘栅场效应晶体管; 晶体管的截止电流或漏电流极低。