公开(公告)号：US06603217B2

公开(公告)日：2003-08-05

申请号：US09967939

申请日：2001-10-02

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H02J100

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/747

摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

公开(公告)号：US06313695B1

公开(公告)日：2001-11-06

申请号：US09301359

申请日：1999-04-29

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G05F110

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/747

摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

摘要翻译： 电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。 差分放大器控制连接到副电源线和次接地线的晶体管。 因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。 因此，可以在保持具有分层供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

公开(公告)号：US5969984A

公开(公告)日：1999-10-19

申请号：US124508

申请日：1998-07-29

申请人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

发明人： Yuichiro Komiya ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H01L29/40 ,  G11C5/14 ,  G11C7/10 ,  G11C11/407 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0944 ,  G11C13/00

CPC分类号： G11C7/1078 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

摘要翻译： 电平转换电路包括第一电流切断电路，第二电流切断电路，电平移位电路和反相器。 第一电流切割电路包括连接到具有升压电位Vpp的节点的两个PMOS晶体管。 第二电流切断电路包括连接到接地节点的两个NMOS晶体管。 电平移位电路包括两个PMOS晶体管和两个NMOS晶体管。 在直流电流在具有升压电位Vpp的节点和接地节点之间流动之前，包括在第一电流切割电路中的任何晶体管和包括在第二电流切割电路中的任何晶体管都被截止。 因此，可以防止具有升压电位Vbb的节点与接地节点之间的电流。

公开(公告)号：US5847595A

公开(公告)日：1998-12-08

申请号：US757861

申请日：1996-11-27

申请人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H03K3/01

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/48 ,  G01R31/31721

摘要： A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode. When external input signals are applied at a predetermined timing, a mode detection signal indicating the test mode is generated, and when the potential at the output node of the internal potential generating circuit has not yet reached the external reference potential, an internal potential is generated and supplied to the output node. Therefore, the internal potential can be controlled in accordance with the external reference potential.

摘要翻译： 半导体存储器件包括：模式检测电路，用于响应于外部输入信号/ RAS，/ CAS和/ WE生成模式检测信号;内部电位产生电路，用于响应于 激活电位控制信号和内部电位控制电路，用于在模式检测信号表示除了测试模式之外的模式的情况下当输出节点的电位尚未达到预定电位时激活电位控制信号，并且 在模式检测信号表示测试模式的情况下，当输出节点的电位尚未达到外部提供的外部参考电位时，激活电位控制信号。 当在预定定时施加外部输入信号时，产生指示测试模式的模式检测信号，并且当内部电位发生电路的输出节点处的电位尚未达到外部参考电位时，产生内部电位 并提供给输出节点。 因此，可以根据外部参考电位来控制内部电位。

公开(公告)号：US5793686A

公开(公告)日：1998-08-11

申请号：US755930

申请日：1996-11-25

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

公开(公告)号：US06522599B2

公开(公告)日：2003-02-18

申请号：US10025857

申请日：2001-12-26

申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

公开(公告)号：US6107700A

公开(公告)日：2000-08-22

申请号：US191121

申请日：1998-11-13

申请人： Masatoshi Ishikawa ,  Tsukasa Ooishi

发明人： Masatoshi Ishikawa ,  Tsukasa Ooishi

IPC分类号： H03K19/00 ,  G05F1/46 ,  G11C11/407 ,  H03K19/0944 ,  H03K19/096 ,  G05F1/10

CPC分类号： G05F1/465 ,  Y10T307/766

摘要： When an operation of an internal circuit is initiated, a current is supplied from an external power supply node to a sub-power source line for a predetermined period. A semiconductor device having a hierarchical power source structure is provided, which can have a voltage variation in the sub-power source line reduced and which can recover the varied voltage speedily to a predetermined voltage level in an operating state of the internal circuit.

摘要翻译： 当启动内部电路的操作时，电流从外部电源节点提供到子电源线一段预定时间段。 提供具有分层电源结构的半导体器件，其可以使子电源线中的电压变化减小，并且可以在内部电路的操作状态下将变化的电压快速恢复到预定的电压电平。

公开(公告)号：US06724686B2

公开(公告)日：2004-04-20

申请号：US10339288

申请日：2003-01-10

申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external dock signal is generated. The input/output buffer circuit is operated in synchronization with the internal dock signal.

摘要翻译： 同步半导体存储器件以单个数据速率SDRAM操作模式与外部时钟信号同步地操作输入/输出缓冲器电路。 在双数据速率SDRAM操作模式中，产生频率为外部停靠信号的两倍的内部时钟信号。 输入/输出缓冲电路与内部停靠信号同步工作。

公开(公告)号：US06337832B1

公开(公告)日：2002-01-08

申请号：US09272194

申请日：1999-03-18

申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

IPC分类号： G11C800

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a frequency two times that of the external clock signal is generated. The input/output buffer circuit is operated in synchronization with the internal clock signal.

公开(公告)号：US06292015B1

公开(公告)日：2001-09-18

申请号：US09272316

申请日：1999-03-19

申请人： Tsukasa Ooishi ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Masatoshi Ishikawa

IPC分类号： H03K1716

CPC分类号： G11C5/147 ,  H03K19/0016

摘要： A semiconductor integrated circuit device has a hierarchical power supply system for a logic circuit. Inverters are provided with power supply from a main power supply line and a sub-power supply line of a higher potential and a main ground line and a sub-ground line of a lower potential. An internal power supply voltage-down converter is placed to set the voltage of the main power supply line higher than a normal operation voltage of the higher potential. An internal supply voltage boosting circuit is placed to set the voltage of the main ground line lower than a normal operation voltage of the lower potential. When respective power supply lines are short-circuited by a switching transistor, the voltage of each power supply line can be maintained at an operation supply voltage.