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114 条记录 (耗时 0.039 秒)

    Integrated circuits with improved spacers and methods for fabricating same
    91.
    发明授权
    Integrated circuits with improved spacers and methods for fabricating same 有权
    具有改进间隔物的集成电路及其制造方法

    公开(公告)号：US08962429B2

    公开(公告)日：2015-02-24

    申请号：US13572343

    申请日：2012-08-10

    申请人： Stefan Flachowsky ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823418 ,  H01L21/823468

    摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes simultaneously shielding a shielded region of a semiconductor substrate and exposing a surface of the shielded region of the semiconductor substrate. An ion implantation is performed to form implant areas in a non-shielded region of the semiconductor substrate adjacent the shielded region. Also, the semiconductor substrate is silicided to form a silicided area in the shielded region of the semiconductor substrate.

    摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括同时屏蔽半导体衬底的屏蔽区域并暴露半导体衬底的屏蔽区域的表面。 执行离子注入以在与屏蔽区域相邻的半导体衬底的非屏蔽区域中形成注入区域。 此外，半导体衬底被硅化以在半导体衬底的屏蔽区域中形成硅化区域。

    Stress enhanced CMOS circuits and methods for their manufacture
    92.
    发明授权
    Stress enhanced CMOS circuits and methods for their manufacture 有权
    应力增强CMOS电路及其制造方法

    公开(公告)号：US08872272B2

    公开(公告)日：2014-10-28

    申请号：US13545624

    申请日：2012-07-10

    申请人： Stefan Flachowsky ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Jan Hoentschel

    IPC分类号： H01L21/31 ,  H01L27/092

    CPC分类号： H01L21/823807 ,  H01L27/092

    摘要： A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.

    摘要翻译： 制造应力增强型CMOS电路的方法包括以第一间距形成第一多个MOS晶体管，并以第二间距形成第二多个MOS晶体管。 第二间距大于第一间距。 该方法还包括沉积覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是沉积在应力增强CMOS电路制造中的唯一应力衬垫。 应力增强型CMOS电路包括以第一间距形成的第一多个MOS晶体管和以第二间距形成的第二多个MOS晶体管。 第二间距大于第一间距。 电路还包括覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是在应力增强CMOS电路上形成的唯一应力衬垫。

    Performance enhancement in transistors by reducing the recessing of active regions and removing spacers
    93.
    发明授权
    Performance enhancement in transistors by reducing the recessing of active regions and removing spacers 有权
    通过减少活性区域的凹陷和去除间隔物来提高晶体管的性能

    公开(公告)号：US08822298B2

    公开(公告)日：2014-09-02

    申请号：US13421242

    申请日：2012-03-15

    申请人： Stefan Flachowsky ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Jan Hoentschel

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864

    摘要： Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.

    摘要翻译： 可以基于优良的工艺顺序形成用于半导体器件的复杂晶体管，其中可以获得紧密间隔的栅极电极结构之间的增加的空间，同时在有源区域中减少材料损耗。 为此，省略了通常用于横向成形漏极和源极延伸区域的偏移间隔物，并且用于深度漏极和源极区域的间隔物可以被完全去除。

    METHODS FOR FABRICATING HIGH CARRIER MOBILITY FINFET STRUCTURES
    95.
    发明申请
    METHODS FOR FABRICATING HIGH CARRIER MOBILITY FINFET STRUCTURES 审中-公开
    用于制造高载波移动性FINFET结构的方法

    公开(公告)号：US20140030876A1

    公开(公告)日：2014-01-30

    申请号：US13560372

    申请日：2012-07-27

    申请人： Stefan Flachowsky ,  Ralf Illgen

    发明人： Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L21/84 ,  H01L21/263

    CPC分类号： H01L21/823821 ,  H01L21/823431 ,  H01L21/845

    摘要： A method for fabricating an integrated circuit having a FinFET structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures. The method further includes removing the silicon oxide formed over the condensed fin structures so as to expose the condensed fin structures.

    摘要翻译： 一种制造具有FinFET结构的集成电路的方法，包括：提供包括硅和高载流子迁移率材料的半导体衬底，在半导体衬底上形成一个或多个鳍结构，以及对衬底进行冷凝处理以使高温 载流子迁移率材料。 冷凝过程导致基本上完全由高载流子迁移率材料形成的冷凝翅片结构的形成和形成在冷凝翅片结构上的氧化硅层。 该方法还包括去除在冷凝翅片结构上形成的氧化硅以暴露冷凝的翅片结构。

    Semiconductor device with dual metal silicide regions and methods of making same
    98.
    发明授权
    Semiconductor device with dual metal silicide regions and methods of making same 有权
    具有双金属硅化物区域的半导体器件及其制造方法

    公开(公告)号：US08558290B2

    公开(公告)日：2013-10-15

    申请号：US13217975

    申请日：2011-08-25

    申请人： Thilo Scheiper ,  Stefan Flachowsky

    发明人： Thilo Scheiper ,  Stefan Flachowsky

    IPC分类号： H01L21/82 ,  H01L29/10 ,  H01L23/051 ,  H01L21/76 ,  H01L29/66 ,  H01L29/76

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

    摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. In one example, the device includes a gate electrode and a plurality of source/drain regions formed in a substrate proximate the gate electrode structure. The device further includes a first metal silicide region formed in each of the source/drain regions, wherein the first metal silicide region has an inner boundary and a second metal silicide region formed in each of the source/drain regions, wherein the second metal silicide region is positioned laterally between the inner boundary of the first metal silicide region and an edge of the gate electrode structure.

    摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 在一个示例中，该器件包括栅电极和形成在靠近栅电极结构的衬底中的多个源/漏区。 该器件还包括形成在每个源极/漏极区域中的第一金属硅化物区域，其中第一金属硅化物区域具有形成在每个源极/漏极区域中的内部边界和第二金属硅化物区域，其中第二金属硅化物 区域横向位于第一金属硅化物区域的内边界和栅电极结构的边缘之间。

    Methods of forming stressed silicon-carbon areas in an NMOS transistor
    99.
    发明授权
    Methods of forming stressed silicon-carbon areas in an NMOS transistor 有权
    在NMOS晶体管中形成应力硅 - 碳区域的方法

    公开(公告)号：US08536034B2

    公开(公告)日：2013-09-17

    申请号：US13216921

    申请日：2011-08-24

    申请人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Ralf Illgen ,  Thilo Scheiper ,  Jan Hoentschel

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/26526 ,  H01L29/7848

    摘要： Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.

    摘要翻译： 这里公开了在NMOS晶体管器件中形成应力硅 - 碳区域的各种方法。 在一个实例中，本文公开的方法包括在包括多个N掺杂区域的半导体衬底的表面上方形成无定形碳层，并对无定形碳层进行离子注入工艺以将碳原子从层 并且将移动的碳原子驱动到衬底中的N掺杂区域中。