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    3D NOR type memory array with wider source/drain conductive lines
    92.
    发明授权
    3D NOR type memory array with wider source/drain conductive lines 有权

    公开(公告)号：US12185531B2

    公开(公告)日：2024-12-31

    申请号：US17412483

    申请日：2021-08-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Wei Jiang ,  Sheng-Chih Lai ,  Feng-Cheng Yang ,  Chung-Te Lin

    IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35

    Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

    FEFET DEVICE
    93.
    发明申请
    FEFET DEVICE 有权

    公开(公告)号：US20240431116A1

    公开(公告)日：2024-12-26

    申请号：US18338414

    申请日：2023-06-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chang Chiang ,  Chung-Te Lin ,  Yu-Ming Lin ,  Po-Ting Lin ,  Yu-Chuan Shih

    IPC: H10B51/30 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

    Memory device and method of forming the same
    94.
    发明授权
    Memory device and method of forming the same 有权

    公开(公告)号：US12176286B2

    公开(公告)日：2024-12-24

    申请号：US17669382

    申请日：2022-02-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Li-Shyue Lai ,  Chien-Hao Huang ,  Chia-Yu Ling ,  Katherine H Chiang ,  Chung-Te Lin

    IPC: H10B51/20 ,  H01L23/522 ,  H01L23/528 ,  H10B51/30

    Abstract: A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING CRYSTALLINE SEMICONDUCTOR FILM
    97.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING CRYSTALLINE SEMICONDUCTOR FILM 有权

    公开(公告)号：US20240387169A1

    公开(公告)日：2024-11-21

    申请号：US18318726

    申请日：2023-05-17

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yen-Chieh Huang ,  I-Cheng Chang ,  Kai-Wen Cheng ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: H01L21/02

    Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate; supplying a first precursor including a first metal element; forming a first layer of a first metal oxide material containing the first metal element over the substrate, wherein the first metal element includes a Group 13 element; supplying a second precursor including a second metal element and a third metal element; forming a second layer of a second metal oxide material that contains the second metal element and the third metal element directly on the first layer to form a crystalline metal oxide semiconductor film containing the first, second and third metal elements, wherein the second metal element and the third metal element are different and each being independently selected from Group 12 elements, Group 13 elements, and Group 15 elements, and the second and third metal elements contained in the second metal oxide material are aligned with the first metal element contained in the first metal oxide material along a vertical crystalline axis direction to form the crystalline metal oxide semiconductor film; forming a source terminal and a drain terminal respectively on and in contact with the crystalline metal oxide semiconductor film; forming a dielectric layer over the substrate; and forming a gate layer on the dielectric layer.

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