公开(公告)号：US20190067572A1

公开(公告)日：2019-02-28

申请号：US16007098

申请日：2018-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Jen Tsai ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

Abstract: A phase change memory (PCM) cell with enhanced thermal isolation and low power consumption is provided. In some embodiments, the PCM cell comprises a bottom electrode, a dielectric layer, a heating element, and a phase change element. The dielectric layer is on the bottom electrode. The heating element extends through the dielectric layer, from a top of the dielectric layer to the bottom electrode. Further, the heating element has a pair of opposite sidewalls laterally spaced from the dielectric layer by a cavity. The phase change element overlies and contacts the heating element. An interface between the phase change element and the heating element extends continuously respectively from and to the opposite sidewalls of the heating element. Also provided is a method for manufacturing the PCM cell.

公开(公告)号：US09991333B1

公开(公告)日：2018-06-05

申请号：US15428678

申请日：2017-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/108 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/92 ,  H01L28/86 ,  H01L28/87 ,  H01L28/88 ,  H01L28/90 ,  H01L28/91

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the MIM capacitor are provided. The MIM capacitor structure includes a substrate. A MIM capacitor is formed on the substrate. The MIM capacitor includes a U-shaped electrode having a first portion. The MIM capacitor also includes an inverted U-shaped electrode. The first portion of the U-shaped electrode is clamped by the inverted U-shaped electrode. The MIM capacitor further includes an insulating film between the U-shaped electrode and the inverted U-shaped electrode.

公开(公告)号：US09917165B2

公开(公告)日：2018-03-13

申请号：US14713462

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11524 ,  H01L21/8239

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/788

Abstract: A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.

公开(公告)号：US09859295B2

公开(公告)日：2018-01-02

申请号：US15425647

申请日：2017-02-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Ting Sung ,  Chung-Chiang Min ,  Wei-Hang Huang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L27/11568 ,  H01L21/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/34 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes forming an oxide layer on a top surface of the conductive layer and removing portions of the conductive layer not covered by the oxide layer to form a memory gate.

公开(公告)号：US20170345835A1

公开(公告)日：2017-11-30

申请号：US15216872

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen

IPC: H01L27/11526 ,  H01L27/11521 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328

Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

公开(公告)号：US20170317095A1

公开(公告)日：2017-11-02

申请号：US15654293

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating gate over a first dielectric on a substrate. A control gate is formed over the floating gate and first and second spacers are formed along sidewalls of the control gate. The first and second spacers extend past outer edges of an upper surface of the floating gate. An etching process is performed on the first and second spacers to remove a portion of the first and second spacers that extends past the outer edges of the upper surface of the floating gate along an interface between the first and second spacers and the floating gate.

公开(公告)号：US20170309816A1

公开(公告)日：2017-10-26

申请号：US15647579

申请日：2017-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L45/00 ,  H01L49/02

CPC classification number: H01L45/1253 ,  H01L28/40 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

公开(公告)号：US09728719B2

公开(公告)日：2017-08-08

申请号：US14261526

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L47/00 ,  H01L45/00 ,  H01L49/02

CPC classification number: H01L45/1253 ,  H01L28/40 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16

Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.

公开(公告)号：US09728545B2

公开(公告)日：2017-08-08

申请号：US14688006

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/105 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11519

CPC classification number: H01L27/11548 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method for manufacturing an embedded flash memory device is provided. Memory and logic shallow trench isolation (STI) regions respectively extend into memory and logic regions of a substrate. The memory and logic STI regions have upper surfaces approximately coplanar with an upper surface of a pad layer overlying the substrate. A capping layer is formed overlying the logic region. A first etch is performed into the pad layer to expose memory gaps between the memory STI regions. A floating gate layer is formed filling the memory gaps. A second, dry etch is performed into the floating gate layer to etch the floating gate layer back to below upper surfaces of the capping layer and the memory STI regions. A third etch is performed into the memory STI regions to recess the memory STI regions. A fourth etch is performed into the floating gate layer to form floating gates.

公开(公告)号：US09660188B2

公开(公告)日：2017-05-23

申请号：US14471082

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-ken Lin ,  Chang-Ming Wu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L29/02 ,  H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1675

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.