公开(公告)号：US07132718B2

公开(公告)日：2006-11-07

申请号：US10726507

申请日：2003-12-04

申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20050176202A1

公开(公告)日：2005-08-11

申请号：US11005015

申请日：2004-12-07

申请人： Digh Hisamoto ,  Kan Yasui

发明人： Digh Hisamoto ,  Kan Yasui

IPC分类号： H01L21/8247 ,  H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/66825

摘要： A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.

摘要翻译： 提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。 当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。 因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

公开(公告)号：US20050095960A1

公开(公告)日：2005-05-05

申请号：US11004991

申请日：2004-12-07

申请人： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

发明人： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

IPC分类号： B24B37/04 ,  B24B41/04 ,  B24B53/12 ,  B24B49/00 ,  B24B1/00

CPC分类号： B24B53/017 ,  B24B37/042 ,  B24B41/04 ,  B24B53/12

摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

摘要翻译： 本发明涉及一种抛光装置以及使用该装置的半导体制造方法。 磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。 此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度， 并且可以总是执行具有较少的面内不均匀性的处理。 因此，修整工具的寿命可以大大延长。 此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。 本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。

公开(公告)号：US06612912B2

公开(公告)日：2003-09-02

申请号：US09371003

申请日：1999-08-10

申请人： Kan Yasui ,  Souichi Katagiri ,  Shigeo Moriyama ,  Yoshio Kawamura ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato

发明人： Kan Yasui ,  Souichi Katagiri ,  Shigeo Moriyama ,  Yoshio Kawamura ,  Ryousei Kawai ,  Sadayuki Nishimura ,  Masahiko Sato

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B1/04 ,  B24B37/042 ,  B24B53/12

摘要： A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.

摘要翻译： 一种制造半导体器件的方法包括：当半导体晶片的凹凸图案通过使用由晶片保持器保持的半导体晶片进行平面化而进行的刷子或超声波的磨石表面激活处理， 磨料颗粒和用于保持磨料颗粒的材料，半导体晶片被相对运动地压在其上。 半导体晶片以高去除率进行处理，并且精确地控制抛光厚度。