公开(公告)号：US08536033B2

公开(公告)日：2013-09-17

申请号：US13233762

申请日：2011-09-15

申请人： Thilo Scheiper ,  Stefan Flachowsky

发明人： Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L21/425

CPC分类号： H01L27/1203 ,  H01L27/1207

摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

公开(公告)号：US20130207275A1

公开(公告)日：2013-08-15

申请号：US13397199

申请日：2012-02-15

申请人： Ricardo P. Mikalo ,  Thilo Scheiper ,  Stefan Flachowsky

发明人： Ricardo P. Mikalo ,  Thilo Scheiper ,  Stefan Flachowsky

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/13091

摘要： Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.

摘要翻译： 本文公开了形成器件级导电触点以改善器件性能的各种方法以及具有这种改进的触发电平触点配置的各种半导体器件。 在一个示例中，本文公开的装置包括定位在第一绝缘材料层中的第一器件级导电触点，其中第一器件级导电触点导电耦合到半导体器件，第二器件级导电触点位于上方并导电耦合 到所述第一器件级触点，其中所述第二器件级触点定位在第二绝缘材料层中，以及用于所述器件的第一布线层，所述第一布线层位于所述第二器件级导电触点的上方并与其导电耦合。

公开(公告)号：US20130049139A1

公开(公告)日：2013-02-28

申请号：US13217792

申请日：2011-08-25

申请人： Steve Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

发明人： Steve Langdon ,  Stefan Flachowsky ,  Thilo Scheiper

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/78654

摘要： Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.

摘要翻译： 本文公开了一种半导体器件，其包括半导体衬底和至少部分地位于半导体衬底中的功函数调整层，所述功函数调整层具有中间部分，相对端部和靠近所述相对的每一个的端部区域 端部和位于功函调整层上方的栅电极。 每个端部区域的最大厚度比工作功能调节层的中间部分的平均厚度大至少25％。

公开(公告)号：US08349695B2

公开(公告)日：2013-01-08

申请号：US12848741

申请日：2010-08-02

申请人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

发明人： Thilo Scheiper ,  Andy Wei ,  Martin Trentzsch

IPC分类号： H01L23/336

CPC分类号： H01L21/823462 ,  H01L21/823857

摘要： In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided.

摘要翻译： 在复杂的制造技术中，工作功能和晶体管元件的阈值电压可以在早期制造阶段通过提供在高k电介质材料内调节物质的功函数来调节，其中栅极电介质材料具有基本上相同的空间分布 不同厚度。 在结合工作功能调整物质之后，可以通过选择性地形成额外的介电层来调节栅极电介质材料的最终厚度，使得栅电极结构的进一步图案化可以以与常规制造高度的相容性来实现 技术 因此，可以避免用于重新调整具有不同厚度栅极电介质材料的晶体管的阈值电压的非常复杂的工艺。

公开(公告)号：US20120241816A1

公开(公告)日：2012-09-27

申请号：US13052772

申请日：2011-03-21

申请人： Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka

发明人： Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas.

摘要翻译： 当形成复杂的P沟道晶体管时，通过以高度可控的方式并入碳和/或氮物质，可以避免含锗应变诱导半导体合金中的金属硅化物附聚或至少显着降低。 在一些说明性实施例中，在外延生长过程中引入碳物质或氮物质，以便形成具有所需氮和/或碳浓度并具有所需厚度的应变诱导半导体合金的表面层，而不会过度影响任何 其他设备区域。

公开(公告)号：US20090321836A1

公开(公告)日：2009-12-31

申请号：US12473610

申请日：2009-05-28

申请人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

发明人： Andy Wei ,  Robert Mulfinger ,  Thilo Scheiper ,  Thorsten Kammler

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

摘要： Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations.

摘要翻译： 可以基于增强的掩模状态形成诸如FinFETS和三栅极晶体管的三维晶体管结构，从而能够在体半导体内以自对准的方式形成漏极和源极区域，鳍片和隔离结构 材料。 在定义基本的翅片结构之后，可以使用平面晶体管配置的高效制造技术，从而进一步提高三维晶体管配置的整体性能。

公开(公告)号：US09023696B2

公开(公告)日：2015-05-05

申请号：US13116672

申请日：2011-05-26

申请人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

发明人： Peter Baars ,  Marco Lepper ,  Thilo Scheiper

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823871

摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.

摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括执行第一处理操作以在半导体衬底的第一区域上方形成第一蚀刻停止层，其中将形成第一类型的晶体管器件，以及形成至少高于第一类型的第一应力诱导层 所述第一区域中的所述蚀刻停止层，其中所述第一应力诱导层适于在所述第一类型晶体管的沟道区域中引起应力。 该方法还包括：在形成第一蚀刻停止层之后，执行第二处理操作，形成第二蚀刻停止层，该第二蚀刻停止层位于衬底的第二区域的第二区域上方，在该第二区域将形成第二类型的晶体管器件，并且形成第二应力诱导层 至少在第二区域中的第二蚀刻停止层上方，其中第二应力诱导层适于在第二类型晶体管的沟道区域中引起应力。 在一个具体示例中，第一和第二蚀刻停止层可以具有相同的近似厚度。

公开(公告)号：US08722500B2

公开(公告)日：2014-05-13

申请号：US13237688

申请日：2011-09-20

申请人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

发明人： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

摘要： Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.

摘要翻译： 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括在替代栅极技术中处理IC，包括在虚拟栅极上形成伪栅极，侧壁间隔物以及金属硅化物触点到有源区域。 填充层被平坦化以暴露伪栅极并且去除虚拟栅极。 形成掩模，其具有覆盖通道区域的从其去除虚拟栅极的一部分的开口和相邻的金属硅化物接触的一部分。 蚀刻填充层和暴露在掩模开口中的侧壁间隔部分，以露出相邻的金属硅化物接触部分。 沉积覆盖沟道区域和暴露的金属硅化物接触的栅电极材料，并被平坦化以形成栅电极和栅极与金属的硅化物接触互连。

公开(公告)号：US08722498B2

公开(公告)日：2014-05-13

申请号：US13209057

申请日：2011-08-12

申请人： Thilo Scheiper ,  Andy Wei

发明人： Thilo Scheiper ,  Andy Wei

IPC分类号： H01L27/105

CPC分类号： H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

摘要： Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

摘要翻译： 在替代栅极方法的上下文中，非平面晶体管（例如FinFET）可以以体积形式形成，其中半导体鳍片在替换栅极序列期间形成。 为此，在一些说明性实施例中，可以在优良的工艺条件的基础上，在早期制造阶段中形成掩埋蚀刻掩模。

公开(公告)号：US08679924B2

公开(公告)日：2014-03-25

申请号：US13017558

申请日：2011-01-31

申请人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

发明人： Andy Wei ,  Vivien Schroeder ,  Thilo Scheiper ,  Thomas Werner ,  Johannes Groschopf

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

摘要翻译： 可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。 因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。 在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。