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124 条记录 (耗时 0.056 秒)

    Method for introducing an equivalent RC circuit in a MOS device using resistive paths
    93.
    发明授权
    Method for introducing an equivalent RC circuit in a MOS device using resistive paths 有权
    使用电阻路径在MOS器件中引入等效RC电路的方法

    公开(公告)号：US06583001B1

    公开(公告)日：2003-06-24

    申请号：US09860217

    申请日：2001-05-18

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L218234

    CPC分类号： H01L21/84 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

    摘要： A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

    摘要翻译： 一种用于提供低功率MOS器件的方法，其包括专门设计成在器件的散装材料和阱连接触点之间提供指定电阻的电阻路径。 通过提供电阻路径，将等效的RC电路引入器件，其允许体材料电势跟踪栅极电位，从而有利地降低器件导通时的阈值电压，并在器件关断时提高阈值电压。 此外，引入电阻路径还允许大量材料电位被控制并且在切换事件之间处于平衡电位下稳定。

    MOS device structure and method for reducing PN junction leakage
    94.
    发明授权
    MOS device structure and method for reducing PN junction leakage 失效
    用于减少PN结泄漏的MOS器件结构和方法

    公开(公告)号：US6137142A

    公开(公告)日：2000-10-24

    申请号：US28472

    申请日：1998-02-24

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L21/761 ,  H01L27/092 ,  H01L27/12 ,  H01L27/01 ,  H01L27/04

    CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L27/1203

    摘要： To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

    摘要翻译： 为了减少在轻掺杂的体材料中形成的轻掺杂阱之间的边界处的p-n结泄漏，在该结处注入高浓度区域。 高浓度区域含有相当高的掺杂剂水平，因此降低了在结处的耗尽区域的宽度。 耗尽区域的减小的宽度又减少了结漏电。

    Tunable threshold SOI device using isolated well structure for back gate
    95.
    发明授权
    Tunable threshold SOI device using isolated well structure for back gate 失效
    可调阈值SOI器件采用隔离阱结构进行后门

    公开(公告)号：US6072217A

    公开(公告)日：2000-06-06

    申请号：US95551

    申请日：1998-06-11

    申请人： James B. Burr

    发明人： James B. Burr

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203

    摘要： To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.

    摘要翻译： 为了降低具有背栅阱的完全耗尽的SOI器件中的阈值电平，器件的沟道区由本征或伪本征半导体形成。 此外，在氧化物层下方形成多个阱结构或隔离区，以减少器件的背栅极阱之间的二极管结泄漏。

    Low power, high performance junction transistor
    96.
    发明授权
    Low power, high performance junction transistor 失效
    低功耗，高性能结晶体管

    公开(公告)号：US5773863A

    公开(公告)日：1998-06-30

    申请号：US292513

    申请日：1994-08-18

    申请人： James B. Burr ,  Michael P. Brassington

    发明人： James B. Burr ,  Michael P. Brassington

    IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/788 ,  H01L29/94

    CPC分类号： H01L29/1083 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/7832 ,  H01L29/7833

    摘要： An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channel region. The transistor further includes a gate region positioned on the surface of the substrate over the channel region, and a buried region of the first conductivity type is positioned within the well region and below the surface of the substrate. The buried region has a dopant concentration of the first conductivity type sufficiently high to slow the growth of source-drain depletion regions and diminish the likelihood of punch through. The buried region may take the form of a buried electrode region or a retrograde well in alternate embodiments. The device is characterized by a gate threshold voltage of at most about 150 mV which can be electrically adjusted using back biasing or floating gate techniques.

    摘要翻译： 描述了需要低功率并且具有高性能的改进的结型晶体管。 晶体管包括衬底，第一导电类型的阱区和由沟道区分隔的第二导电类型的源区和漏区。 晶体管还包括位于沟道区域上的衬底表面上的栅极区域，并且第一导电类型的掩埋区域位于阱区域内并在衬底的表面下方。 掩埋区域具有足够高的第一导电类型的掺杂剂浓度，以减缓源 - 漏耗尽区的生长并减少穿通的可能性。 在替代实施例中，掩埋区域可以采取掩埋电极区域或逆行井的形式。 该器件的特征在于栅极阈值电压至多约150mV，其可以使用反向偏置或浮动栅极技术进行电气调节。

    Back-biasing in asymmetric MOS devices
    97.
    发明授权
    Back-biasing in asymmetric MOS devices 失效
    非对称MOS器件的反偏置

    公开(公告)号：US5753958A

    公开(公告)日：1998-05-19

    申请号：US543485

    申请日：1995-10-16

    申请人： James B. Burr ,  Douglas Alan Laird

    发明人： James B. Burr ,  Douglas Alan Laird

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/66659 ,  H01L29/1087

    摘要： An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

    摘要翻译： 本文公开了具有不对称袋区域的可调阈值电压MOS器件。 口袋区域邻近装置的通道区域邻近源极或漏极之一。 口袋区域具有与器件体积相同的导电类型（尽管具有较高的掺杂剂浓度），当然还有与器件的源极和漏极相反的导电类型。 具有这样的口袋区域的MOS器件可以通过将电位直接施加到其口袋区域来调节其阈值电压。 该能力通过提供电耦合到口袋区域的接触或导电接头来实现。 这种“袖带”也电耦合到金属化线（器件外部），该金属化线可以保持在与设备反偏特定量所需的电位相对应的指定电位。

    Dynamic chip control
    99.
    发明授权
    Dynamic chip control 有权
    动态芯片控制

    公开(公告)号：US09081566B2

    公开(公告)日：2015-07-14

    申请号：US13037042

    申请日：2011-02-28

    申请人： Kleanthes G. Koniaris ,  James B. Burr ,  Mark Hennecke

    发明人： Kleanthes G. Koniaris ,  James B. Burr ,  Mark Hennecke

    IPC分类号： G06F1/32 ,  G05B13/02 ,  G06F1/20

    CPC分类号： G06F1/3203 ,  G05B13/026 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

    摘要： Methods and systems for operating a semiconductor device (e.g., a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.

    摘要翻译： 描述了用于操作半导体器件（例如，微处理器）的方法和系统。 微处理器最初以在任何器件温度下处于操作限度内的电压和频率运行。 使用将设备温度，工作限制和功耗与电压和频率相关联的型号，可以选择电源电压和新的工作频率。 此后，定期咨询这些型号以继续调整电源电压和工作频率，以使微处理器在非常接近其容量的情况下工作，特别是在例如执行处理器密集型指令的情况下。

    SOFTWARE CONTROLLED TRANSISTOR BODY BIAS
    100.
    发明申请
    SOFTWARE CONTROLLED TRANSISTOR BODY BIAS 有权
    软件控制晶体管体偏置

    公开(公告)号：US20140033160A1

    公开(公告)日：2014-01-30

    申请号：US13741246

    申请日：2013-01-14

    申请人： David R. Ditzel ,  James B. Burr

    发明人： David R. Ditzel ,  James B. Burr

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.

    摘要翻译： 软件控制晶体管体偏置。 访问目标频率。 使用软件，为了提高电路的特性，确定了目标频率的晶体管体偏置值。 晶体管的主体基于主体偏置值被偏置，其中特性被增强。