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    Image-pickup semiconductor device having a lens, a light-receiving element and a flexible substrate therebetween with a shading plate blocking undesired light rays
    91.
    发明授权
    Image-pickup semiconductor device having a lens, a light-receiving element and a flexible substrate therebetween with a shading plate blocking undesired light rays 有权
    具有透镜，光接收元件和其间的柔性基板的摄像半导体器件具有阻挡不期望的光线的遮光板

    公开(公告)号：US06476417B2

    公开(公告)日：2002-11-05

    申请号：US09818523

    申请日：2001-03-28

    申请人： Toshiyuki Honda ,  Susumu Kida ,  Hideo Suzuki

    发明人： Toshiyuki Honda ,  Susumu Kida ,  Hideo Suzuki

    IPC分类号： H01L2904

    CPC分类号： H01L27/14625 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L2924/0002 ,  Y10S257/911 ,  H01L2924/00

    摘要： A semiconductor device for picking up an image includes a lens-mounting unit provided with a lens for picking up an image; a semiconductor chip having a light-receiving element formed on a circuit-forming surface thereof, the light-receiving element converting light from the lens into an image signal; a flexible substrate provided between the lens-mounting unit and the semiconductor chip so as to supply the image signal to an external circuit; and a shading plate blocking light transmitting through the flexible substrate toward the semiconductor chip so as to substantially remove an influence of the light on the light-receiving element.

    摘要翻译： 用于拍摄图像的半导体装置包括具有用于拾取图像的透镜的透镜安装单元; 具有形成在其电路形成表面上的光接收元件的半导体芯片，所述光接收元件将来自所述透镜的光转换为图像信号; 设置在透镜安装单元和半导体芯片之间的柔性基板，以将图像信号提供给外部电路; 以及遮光板，其阻挡透过柔性基板朝向半导体芯片的光，以便基本上消除光对光接收元件的影响。

    Nonvolatile semiconductor memory device capable of conditioning over-erased memory cells
    93.
    发明授权
    Nonvolatile semiconductor memory device capable of conditioning over-erased memory cells 失效
    能够调节过度擦除的存储单元的非易失性半导体存储器件

    公开(公告)号：US5920509A

    公开(公告)日：1999-07-06

    申请号：US888307

    申请日：1997-07-03

    申请人： Hiroshige Hirano ,  Toshiyuki Honda

    发明人： Hiroshige Hirano ,  Toshiyuki Honda

    IPC分类号： G11C16/34 ,  G11C16/06

    CPC分类号： G11C16/3409 ,  G11C16/3404

    摘要： By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

    摘要翻译： 通过将全部组反转控制栅极设置为逻辑电压“H”，存储单元阵列块的所有位线上的存储单元连接到反向电压供应电路，从而执行组反转操作。 当组反转控制门中的一个被设置为逻辑电压“H”时，具有偶数或奇数个存储单元阵列块的位线上的存储单元连接到反向电压供应电路，使得部分组 执行反转操作。 当列选择门之一被设置为逻辑电压“H”时，所选择的位线连接到反向电压供应电路。 因此，执行连接到所选位线的存储单元的线路反向操作。 因此，可以实现完全控制存储单元的截止电流的高速反转操作，并且可以通过改变用于执行反转操作的操作单元来实现低电压操作。

    Information processing apparatus, nonvolatile storage device, information porcessing system and nonvolatile memory controller
    94.
    发明授权
    Information processing apparatus, nonvolatile storage device, information porcessing system and nonvolatile memory controller 有权
    信息处理装置，非易失性存储装置，信息处理系统和非易失性存储器控制器

    公开(公告)号：US09007864B2

    公开(公告)日：2015-04-14

    申请号：US13037683

    申请日：2011-03-01

    申请人： Toshiyuki Honda

    发明人： Toshiyuki Honda

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected to the voltage line and which outputs the first voltage or a second voltage that is lower than the first voltage, a host IO driver for driving a data line with the output of the host regulator as a power source, a host voltage detection circuit for detecting whether the voltage of the data line is the second voltage or a voltage that is higher than the second voltage, and a host control unit for detecting a mismatch of interface voltages between the host device and a memory card based on the output voltage of the host regulator and the detection result of the host voltage detection circuit.

    摘要翻译： 主机设备包括电压源，其经由主电压开关连接到电压线并向电压线提供第一电压;主电压调节器，连接到电压线并输出第一电压或第二电压 低于第一电压的主机IO驱动器，用于以主机调节器的输出驱动数据线作为电源的主机IO驱动器，用于检测数据线的电压是否为第二电压的主机电压检测电路或电压 以及主机控制单元，用于基于主机调节器的输出电压和主机电压检测电路的检测结果来检测主机设备和存储卡之间的接口电压的不匹配。

    Memory controller and non-volatile storage device
    95.
    发明授权
    Memory controller and non-volatile storage device 有权
    内存控制器和非易失性存储设备

    公开(公告)号：US08856427B2

    公开(公告)日：2014-10-07

    申请号：US13435493

    申请日：2012-03-30

    申请人： Hirokazu So ,  Toshiyuki Honda

    发明人： Hirokazu So ,  Toshiyuki Honda

    IPC分类号： G06F12/02 ,  G06F11/10

    CPC分类号： G06F11/1068

    摘要： A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address.

    摘要翻译： 非易失性存储设备包括用于存储数据的非易失性存储器; 以及用于执行非易失性存储器的控制的存储器控​​制器。 存储器控制器存储第二纠错码以及存储在同一页数据中的第一纠错码。 当写入小于预定义大小的数据时，存储器控制器不添加第二纠错码，并将数据和第一校正码的双工数据存储在不同的页面中。 存储器控制器在读取时使用第一和/或第二校正码校正数据。 有效数据管理表管理哪个逻辑块相对于相同的逻辑地址存储有效数据。

    Nonvolatile memory device and memory controller
    96.
    发明授权
    Nonvolatile memory device and memory controller 有权
    非易失性存储器件和存储器控制器

    公开(公告)号：US08738974B2

    公开(公告)日：2014-05-27

    申请号：US12870159

    申请日：2010-08-27

    申请人： Toshiyuki Honda

    发明人： Toshiyuki Honda

    IPC分类号： G06F11/00

    CPC分类号： G06F11/141 ,  G06F11/1441 ,  G11C2029/0411

    摘要： The memory controller writes and reads data in and from a nonvolatile memory. The nonvolatile memory has a plurality of memory cell blocks, each memory cell block includes a plurality of multi-level cells each capable of storing m-bit data (m is a natural number of two or more), a first page to a m-th page are allocated to the respective m bits of the multi-level cell, the memory controller sequentially writes the data to the memory cells from the first page in ascending order, and comprises a backup unit, and when a write command is received from the outside of the memory controller, in a case where a data write destination of the data in the nonvolatile memory is a n-th (n is a natural number of two to m) page of the multi-level cell, and data is already written in the first to (n-1)th pages, the backup unit copies the already written data to a nonvolatile storable backup region.

    摘要翻译： 存储器控制器将数据写入和读出非易失性存储器。 非易失性存储器具有多个存储单元块，每个存储单元块包括多个多电平单元，每个多电平单元能够存储m位数据（m是两个或多个自然数），第一页到第m- 分配给多级单元的各个m位时，存储器控制器以升序顺序地将数据从第一页写入存储器单元，并且包括备份单元，并且当从第一页接收到写命令时， 在存储器控制器的外部，在非易失性存储器中的数据的数据写入目的地是多级单元的第n（n是2到m的自然数）页面并且数据已被写入的情况下 在第一到第（n-1）页中，备份单元将已写入的数据复制到非易失性可存储备份区。

    Nonvolatile memory device and nonvolatile memory system with fast boot capability
    97.
    发明授权
    Nonvolatile memory device and nonvolatile memory system with fast boot capability 有权
    非易失性存储器件和具有快速启动能力的非易失性存储器系统

    公开(公告)号：US08527691B2

    公开(公告)日：2013-09-03

    申请号：US12665064

    申请日：2008-07-30

    申请人： Toshiyuki Honda ,  Masayuki Toyama ,  Masahiro Nakanishi

    发明人： Toshiyuki Honda ,  Masayuki Toyama ,  Masahiro Nakanishi

    IPC分类号： G06F13/00

    CPC分类号： G06F9/4403 ,  G06F12/0246 ,  G06F2212/7201

    摘要： A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device.

    摘要翻译： 非易失性存储装置包括控制器和非易失性存储器。 控制器具有：逻辑 - 物理地址转换部分，用于将由主机设备指定的逻辑地址转换成物理地址; 以及引导代码地址转换部分，用于将由主机设备指定的引导代码地址信息转换为物理地址。 在上电之后并且在逻辑 - 物理地址转换部分变得可用之前，通过从外部指定引导代码地址信息从主机设备指定逻辑地址可以访问的区域的一部分读取引导代码 。 因此，可以在通电之后快速启动非易失性存储器系统。 在可以使用逻辑 - 物理地址转换部分的状态下，通过从主机设备指定逻辑地址来执行数据读取和数据写入。

    Semiconductor memory apparatus and method for writing data into the flash memory device
    98.
    再颁专利
    Semiconductor memory apparatus and method for writing data into the flash memory device 有权
    用于将数据写入闪速存储器件的半导体存储装置和方法

    公开(公告)号：USRE42648E1

    公开(公告)日：2011-08-23

    申请号：US12016751

    申请日：2003-08-25

    申请人： Yoshihisa Inagaki ,  Toshiyuki Honda

    发明人： Yoshihisa Inagaki ,  Toshiyuki Honda

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7203

    摘要： A source block (B0) and the logical page number (“8”) of a write target page are identified from the logical address of the write target page. Data objects (DN8, DN9, . . . , DN12) to be written, which a host stores in a page buffer (2), are written into the data areas (DA) of the pages (Q0, Q1, . . . , Q4) of a destination block (Bn), starting from the top page (Q0) in sequence. The logical page number (“8”) of the write target page is written into the redundant area (RA) of the top page (Q0). The physical page number (“6=8−2”) of the write target page is identified, based on the logical page number (“8”) of the write target page and the page offset (“2”) of the source block (B0). When notified by the host of the end of the sending of the data objects (DN8, . . . , DN12), the data items (D13, . . . , D31, D0, D1, . . . , D7) in the source block (B0) are transferred to the pages (Q5, Q6, . . . , Q31) in the destination block (Bn) via the page buffer (2) sequentially and cyclically, starting from the page (P11) situated cyclically behind the write target page (P6) by the number (“5”) of pages of the data objects (DN8, . . . , DN12).

    摘要翻译： 从写入目标页面的逻辑地址识别写入目标页面的源块（B0）和逻辑页码（“8”）。 将主机存储在页面缓冲器（2）中的要写入的数据对象（DN8，DN9，...，DN12）被写入页面（Q0，Q1，...）的数据区域（DA） Q4），从首页（Q0）开始。 写目标页面的逻辑页码（“8”）被写入首页（Q0）的冗余区域（RA）。 基于写目标页的逻辑页数（“8”）和源块的页偏移（“2”），识别写目标页的物理页号（“6 = 8-2”） （B0）。 当主机通知数据对象（DN8，...，DN12）的发送结束时，源中的数据项（D13，...，D31，D0，D1，...，D7） 块（B0）从循环地位于写入后面的页（P11）开始，顺序地循环地经由页缓冲器（2）被传送到目的地块（Bn）中的页（Q5，Q6，... Q31） 目标页面（P6）由数据对象（DN8，...，DN12）的页数（“5”）。