公开(公告)号：US08350162B2

公开(公告)日：2013-01-08

申请号：US12659556

申请日：2010-03-12

Applicant: Hyun Tae Kim ,  Tae Sang Park ,  Young Jun Moon ,  Soon Min Hong ,  Hyo Young Shin

Inventor： Hyun Tae Kim ,  Tae Sang Park ,  Young Jun Moon ,  Soon Min Hong ,  Hyo Young Shin

IPC: H05K1/11

CPC classification number: H05K3/363 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2201/09709 ,  H05K2201/10666 ,  H05K2203/0195 ,  H05K2203/167 ,  Y10T29/49126 ,  Y10T29/49213

Abstract: Disclosed is a connection structure for a circuit board using a solder bump to arrange circuit boards. The circuit board connection structure includes a solder bump prepared on one of two circuit boards and a perforated part formed at the other of the circuit boards to receive the solder bump. Facing both circuit boards towards each other and inserting the solder bump into the perforated part, the circuit boards are desirably arranged.

Abstract translation: 公开了一种使用焊料凸块布置电路板的电路板的连接结构。 电路板连接结构包括制备在两个电路板中的一个上的焊料凸块和形成在另一个电路板上的穿孔部分以接收焊料凸块。 将两个电路板朝向彼此并将焊料凸块插入穿孔部分中，期望布置电路板。

公开(公告)号：US08143709B2

公开(公告)日：2012-03-27

申请号：US12474429

申请日：2009-05-29

Applicant: Hye-Jin Kim

Inventor： Hye-Jin Kim

IPC: H01L23/02

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package having a solder ball having a double connection structure which reduces a total height of a package on package (POP). The semiconductor package includes a first semiconductor package in which a semiconductor device is mounted on a lower surface of a first substrate, and a through hole is formed in a solder ball pad region of the first substrate, a second semiconductor package in which a semiconductor device is mounted on an upper surface of a second substrate, and a solder ball pad of the second substrate is formed to correspond to the through hole of the first substrate and is mounted on the first substrate, and a common solder ball that is disposed below the first substrate and is connected to the solder ball pad of the second substrate through the through hole.

Abstract translation: 一种具有双重连接结构的焊球的半导体封装，其减少了封装（POP）上的封装的总高度。 半导体封装包括第一半导体封装，其中半导体器件安装在第一衬底的下表面上，并且通孔形成在第一衬底的焊球焊盘区域中;第二半导体封装，其中半导体器件 安装在第二基板的上表面上，并且形成第二基板的焊球垫，以对应于第一基板的通孔，并且安装在第一基板上，并且配置公共焊球， 并且通过通孔与第二基板的焊球焊盘连接。

公开(公告)号：US20110278725A1

公开(公告)日：2011-11-17

申请号：US13192683

申请日：2011-07-28

Applicant: Cheng-Lien CHIANG

Inventor： Cheng-Lien CHIANG

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/4826 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/144 ,  H05K1/181 ,  H05K3/244 ,  H05K3/368 ,  H05K2201/09036 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/10234 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2203/041 ,  H05K2203/0455 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads.

Abstract translation: 公开了电镀通孔之间的互连机构，第一实施例包括具有第一电镀通孔的第一基板; 具有第二电镀通孔的第二基板; 金属芯构造在两个电镀通孔之间; 金属球的直径大于电镀通孔的直径; 并且熔化的焊料结合第一电镀通孔，金属芯和第二电镀通孔。 第二实施例包括具有仅在电镀通孔的环形垫上镀金的堆叠衬底; 熔化的焊料结合两个金环垫。

公开(公告)号：US08030574B2

公开(公告)日：2011-10-04

申请号：US12150265

申请日：2008-04-25

Applicant: Wen-Bin Lin ,  Chih-Hung Chang

Inventor： Wen-Bin Lin ,  Chih-Hung Chang

IPC: H05K1/00

CPC classification number: H05K1/118 ,  H05K1/028 ,  H05K1/117 ,  H05K3/363 ,  H05K2201/0949 ,  H05K2201/10666 ,  H05K2203/0191 ,  H05K2203/1572

Abstract: A flexible printed circuit includes a flexible substrate, a plurality of first conductive wires, and a plurality of second conductive wires. The flexible substrate includes a first surface and a second surface facing the first surface. The first conductive wires are provided on the first surface. The first conductive wires extend from an edge of the flexible substrate to another edge of the flexible substrate. The second conductive wires are provided on the second surface. The second conductive wires extend from an end of the flexible substrate to a predetermined portion of the flexible substrate. A part of each second conductive wire at the predetermined portion of the flexible substrate is electrically connected with the first conductive wire via a conductive structure.

Abstract translation: 柔性印刷电路包括柔性基板，多个第一导电线和多个第二导线。 柔性基板包括第一表面和面向第一表面的第二表面。 第一导电线设置在第一表面上。 第一导线从柔性基板的边缘延伸到柔性基板的另一边缘。 第二导线设置在第二表面上。 第二导线从柔性基板的端部延伸到柔性基板的预定部分。 在柔性基板的预定部分处的每个第二导线的一部分经由导电结构与第一导线电连接。

公开(公告)号：US08015703B2

公开(公告)日：2011-09-13

申请号：US12081835

申请日：2008-04-22

Applicant: Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

Inventor： Hitoki Kanagawa ,  Tetsuya Ohsawa ,  Yasunari Ooyabu

IPC: H01R9/00 ,  H05K3/00

CPC classification number: H05K1/112 ,  G11B5/4833 ,  H01L2224/11003 ,  H01L2224/742 ,  H05K1/056 ,  H05K3/06 ,  H05K3/244 ,  H05K3/28 ,  H05K3/363 ,  H05K3/44 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/10666 ,  H05K2203/0323 ,  H05K2203/041 ,  H05K2203/0455 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: A method of manufacturing a wired circuit board including a metal supporting board. An insulating layer is formed on the metal supporting board in a pattern in which concave portions are formed. A conductive pattern in a pattern having terminals for connecting with external terminals via a molten metal is formed on the metal supporting board and the insulating layer. The terminals include shoulder portions corresponding to the concave portions and are concaved downward from an upper surface. First through holes penetrate the terminals in a thickness direction thereof Second through holes are formed communicating with the first through holes in portions of the insulating layer corresponding to the terminals by removing the concave portions to expose a lower surface of the terminals such that the second through holes penetrate the insulating layer in a thickness direction thereof and have a diameter larger than that of the first through holes.

Abstract translation: 一种制造包括金属支撑板的布线电路板的方法。 绝缘层以形成有凹部的图案形成在金属支撑板上。 在金属支撑板和绝缘层上形成具有用于经由熔融金属与外部端子连接的端子的图案中的导体图案。 端子包括对应于凹部的肩部，并且从上表面向下凹入。 第一通孔在厚度方向上贯穿端子。通过除去凹部以露出端子的下表面，在绝缘层的与端子对应的部分中的第一通孔形成第二通孔，以使第二通孔 孔的厚度方向穿过绝缘层，其直径大于第一通孔的直径。

公开(公告)号：US07944710B2

公开(公告)日：2011-05-17

申请号：US12528443

申请日：2008-10-06

Applicant: Victor Marten ,  Aakar Patel ,  Mark Vanstone

Inventor： Victor Marten ,  Aakar Patel ,  Mark Vanstone

IPC: H05K1/11

CPC classification number: H05K3/363 ,  H05K1/165 ,  H05K3/3447 ,  H05K3/368 ,  H05K2201/096 ,  H05K2201/10303 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49165

Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.

Abstract translation: 本公开涉及使用相对较小的空间并提供低电阻连接将平面感应元件的绕组PCB有效地端接到主PCB。 所公开的方法特别适用于其中几个绕组PCB，和/或绕组PCB和主PCB都由磁路部件封闭的平面结构。 这些方法允许绕组PCB简单地搁置在主PCB或其他绕组PCB上，没有任何间隙。 本公开采用配套的导电环形环，其具有可选的互锁端子销，其允许两个PCB固定地耦合在一起，同时保持两个PCB的焊接掩模层之间的最小距离，以防止形成不需要的电连接 在两个PCB之间。 焊接用于确保配合环形圈和可选端子销的每个组件中的有效耦合。

公开(公告)号：US20110084383A1

公开(公告)日：2011-04-14

申请号：US12903403

申请日：2010-10-13

Applicant: Daisuke MIZUTANI

Inventor： Daisuke MIZUTANI

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H05K1/147 ,  H01L21/76898 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/222 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09063 ,  H05K2201/092 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.

Abstract translation: 半导体器件包括：第一电路基体部件，其包括形成有多个第一电极的表面;第二电路基体部件，设置在第一电路基体的上方，并具有分别形成在第一电极上方的第一通孔和第二通孔; 设置在第二电路基体上方的封装，以及设置在第一通孔内的多个第一凸起和第二通孔，以将第一电极连接到半导体封装。

公开(公告)号：US20100327436A1

公开(公告)日：2010-12-30

申请号：US12828175

申请日：2010-06-30

Applicant: Mark MOSHAYEDI

Inventor： Mark MOSHAYEDI

IPC: H01L23/498 ,  H01L23/52

CPC classification number: H05K1/181 ,  H01L23/50 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/0949 ,  H05K2201/10515 ,  H05K2201/10666 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Abstract translation: 多芯片堆叠模块为给定的表面芯片占用空间提供了增加的电路密度。 支撑结构与标准表面贴装型芯片交替形成堆叠，其中支撑结构将芯片电互连。 一个方面是用于在垂直堆叠中互连多个大致平面的芯片的结构和方法，使得在堆叠中共同连接的芯片的信号和单独访问的信号在堆栈内分离。

公开(公告)号：US07709929B2

公开(公告)日：2010-05-04

申请号：US11501065

申请日：2006-08-09

Applicant: Kouichi Kuramitsu ,  Kazuo Fujita ,  Noboru Izuhara

Inventor： Kouichi Kuramitsu ,  Kazuo Fujita ,  Noboru Izuhara

IPC: H01L29/00

CPC classification number: H05K1/0231 ,  H01L23/66 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/113 ,  H05K1/141 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/10666 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/0733

Abstract: A disclosed capacitor sheet attached to an electronic apparatus comprises: a laminated body; a first penetration electrode penetrating the laminated body, the first penetration electrode being electrically connected to a terminal electrode of the electronic apparatus; a second penetration electrode disposed at an arrangement position different from that of the first penetration electrode on the laminated body, the second penetration electrode being electrically insulated from the first penetration electrode and penetrating the laminated body; at least one first conductor thin film electrically connected to the first penetration electrode and insulated from the second penetration electrode; and at least one second conductor thin film disposed so as to face the first conductor thin film via a dielectric layer, the second conductor thin film being electrically connected to the second penetration electrode and insulated from the first penetration electrode.

Abstract translation: 所公开的电容器片附接到电子设备包括：层叠体; 穿过层叠体的第一穿透电极，第一穿透电极电连接到电子设备的端子电极; 第二穿透电极，其设置在层叠体上与第一穿透电极不同的配置位置，第二穿透电极与第一穿透电极电绝缘并穿透层叠体; 电连接到第一穿透电极并与第二穿透电极绝缘的至少一个第一导体薄膜; 以及至少一个第二导体薄膜，其经由电介质层设置为面对所述第一导体薄膜，所述第二导体薄膜电连接到所述第二穿透电极并与所述第一穿透电极绝缘。

公开(公告)号：US07612296B2

公开(公告)日：2009-11-03

申请号：US11216813

申请日：2005-08-31

Applicant: Meta Rohde ,  Ajay Kumar Poddar ,  Klaus Juergen Schoepf ,  Reimund Rebel

Inventor： Meta Rohde ,  Ajay Kumar Poddar ,  Klaus Juergen Schoepf ,  Reimund Rebel

IPC: H01R12/04 ,  H05K1/00

CPC classification number: H05K3/3442 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/244 ,  H05K3/368 ,  H05K2201/09481 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49165

Abstract: A printed circuit board having one or more vias disposed in the surface area of a pad. The pad may serve as a connection point between the printed circuit board and another circuit board and is disposed along the edge of the board such that the vias do not form half vias.

Abstract translation: 具有设置在垫的表面区域中的一个或多个通孔的印刷电路板。 垫可以用作印刷电路板和另一个电路板之间的连接点，并且沿着板的边缘布置，使得通孔不形成半通孔。