Magnetic tunnel junction with compensation element
    91.
    发明授权
    Magnetic tunnel junction with compensation element 有权
    带有补偿元件的磁隧道结

    公开(公告)号:US08508988B2

    公开(公告)日:2013-08-13

    申请号:US13527845

    申请日:2012-06-20

    IPC分类号: G11C11/00

    CPC分类号: G11C11/161

    摘要: A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co100-X-YFeXBY wherein X is a value being greater than 30 and Y is a value being greater than 15.

    摘要翻译: 公开了一种具有补偿元件的磁性隧道结。 磁性隧道结包括参考元件和补偿元件,该补偿元件具有与参考元件的磁化矩相反的磁化力矩。 自由磁性层在参考元件和补偿元件之间,并且电绝缘和非磁性隧道势垒层将自由磁性层与参考元件分开。 自由磁性层包括Co100-X-YFeXBY,其中X是大于30的值,Y是大于15的值。

    Tunable random bit generator with magnetic tunnel junction
    92.
    发明授权
    Tunable random bit generator with magnetic tunnel junction 有权
    具有磁隧道结的可调随机位发生器

    公开(公告)号:US08495118B2

    公开(公告)日:2013-07-23

    申请号:US12399127

    申请日:2009-03-06

    IPC分类号: G06F7/58 G11C11/00 G11C7/00

    摘要: A random number generator device that utilizes a magnetic tunnel junction. An AC current source is in electrical connection to the magnetic tunnel junction to provide an AC current having an amplitude and a frequency through the free layer of the magnetic tunnel junction, the AC current configured to switch the magnetization orientation of the free layer via thermal magnetization. A read circuit is used to determine the relative orientation of the free layer magnetization in relation to the reference layer magnetization orientation.

    摘要翻译: 利用磁性隧道结的随机数发生装置。 AC电流源与磁性隧道结电连接以提供具有通过磁性隧道结的自由层的振幅和频率的AC电流,AC电流被配置为通过热磁化来切换自由层的磁化取向 。 读取电路用于确定自由层磁化相对于参考层磁化取向的相对取向。

    Distributed brillouin sensing systems and methods using few-mode sensing optical fiber
    93.
    发明授权
    Distributed brillouin sensing systems and methods using few-mode sensing optical fiber 有权
    分布式布里渊传感系统和使用多模感光光纤的方法

    公开(公告)号:US08493556B2

    公开(公告)日:2013-07-23

    申请号:US13344065

    申请日:2012-01-05

    IPC分类号: G01N21/00

    CPC分类号: G01K11/32 G01L1/246

    摘要: Some embodiments of a distributed Brillouin optical fiber sensing system employs a sensing optical fiber that supports two or more (i.e., few) guided modes. Pump light supported by one of the guided modes is used to form a dynamic Brillouin grating (DBG). Probe light supported by at least one of the other guided modes interacts with the DBG to form reflected probe light that is received and analyzed to determine a Brillouin frequency shift, a phase matching wavelength between probe and pump light, a reflection location, which in turn allows for making a measurement of at least one condition along the sensing optical fiber. Supporting the pump and probe light in different guided modes results in the optical fiber sensing system being able to simultaneously measure temperature and strain and having a higher spatial resolution than sensing systems where the pump light and probe light share a common guided mode.

    摘要翻译: 分布式布里渊光纤感测系统的一些实施例采用支持两个或更多(即少数)导模的传感光纤。 由一个引导模式支持的泵浦光用于形成动态布里渊光栅(DBG)。 由其他引导模式中的至少一个支撑的探测光与DBG相互作用以形成被接收和分析的反射探测光,以确定布里渊频移,探针与泵浦光之间的相位匹配波长,反射位置 允许沿着感测光纤测量至少一个条件。 以不同的导向模式支持泵浦和探测光,导致光纤感测系统能够同时测量温度和应变,并且具有比泵浦光和探针光共享共同引导模式的感测系统更高的空间分辨率。

    DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH
    94.
    发明申请
    DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH 有权
    具有通道停止电位器的双栅氧化物晶体管MOSFET

    公开(公告)号:US20130175612A1

    公开(公告)日:2013-07-11

    申请号:US13780579

    申请日:2013-02-28

    IPC分类号: H01L29/78

    摘要: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

    摘要翻译: 公开了半导体器件和制造方法。 该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。 第一栅极流道形成在基板中并电连接到栅电极,其中第一栅极流道围绕有源区。 第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。 终端结构围绕第一和第二栅极流道和有源区域。 端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料,其中端接结构电气短路到衬底的源极或体层,从而形成用于器件的通道停止。

    MOS device with varying contact trench lengths
    96.
    发明授权
    MOS device with varying contact trench lengths 有权
    具有不同接触沟槽长度的MOS器件

    公开(公告)号:US08450794B2

    公开(公告)日:2013-05-28

    申请号:US13316365

    申请日:2011-12-09

    摘要: A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.

    摘要翻译: 半导体器件形成在半导体衬底上。 该装置包括排水管; 覆盖漏极的外延层; 设置在外延层中的主体,具有主体顶表面和主体底表面; 嵌入在体内的源体,从身体顶面延伸到体内; 延伸到所述外延层中的第一栅极沟槽; 设置在所述第一栅极沟槽中的第一栅极; 有源区域接触沟槽,其延伸穿过源极和至少部分本体进入漏极; 有源区接触电极,设置在有源区接触沟槽内; 延伸到所述外延层中的第二栅极沟槽; 设置在所述栅极沟槽中的第二栅极; 形成在第二栅极内的栅极接触沟槽; 以及设置在所述栅极接触沟槽内的栅极接触电极。

    Magnetic field assisted stram cells
    97.
    发明授权
    Magnetic field assisted stram cells 失效
    磁场辅助电极

    公开(公告)号:US08400825B2

    公开(公告)日:2013-03-19

    申请号:US13491891

    申请日:2012-06-08

    IPC分类号: G11C11/00

    CPC分类号: G11C11/1675 G11C11/1659

    摘要: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.

    摘要翻译: 具有磁隧道结电池的存储单元,其利用自旋转矩和电流感应磁场来辅助磁性隧道结电池自由层的磁化取向的切换。 存储单元包括用于使电流通过磁性隧道结单元的自旋转矩电流源,该自旋转矩电流源具有与磁化方位垂直的方向,并且还包括磁安培励磁电流源在正交或 与磁化方向成一定角度。

    Asymmetric write current compensation
    98.
    发明授权
    Asymmetric write current compensation 有权
    不对称写入电流补偿

    公开(公告)号:US08320169B2

    公开(公告)日:2012-11-27

    申请号:US13333598

    申请日:2011-12-21

    IPC分类号: G11C11/00

    摘要: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

    摘要翻译: 一种用于补偿非易失性单元中不对称写入电流的装置和方法。 单位单元包括开关装置和非对称电阻感测元件(RSE),诸如非对称电阻随机存取存储器(RRAM)元件或非对称自旋转矩传递随机存取存储器(STRAM)元件。 RSE相对于开关装置在物理上定位在单位单元内,使得用于编程RSE的硬方向与单元单元的简单编程方向对齐,并且用于编程RSE的简单方向与硬方向对齐 编程单元格

    Wide and Deep Oxide Trench in A Semiconductor Substrate with Interspersed Vertical Oxide Ribs
    99.
    发明申请
    Wide and Deep Oxide Trench in A Semiconductor Substrate with Interspersed Vertical Oxide Ribs 有权
    半导体衬底中的宽和深氧化物沟槽,具有散射的垂直氧化物肋

    公开(公告)号:US20120261791A1

    公开(公告)日:2012-10-18

    申请号:US13537493

    申请日:2012-06-29

    IPC分类号: H01L21/76 H01L23/58

    摘要: A semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD is disclosed. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

    摘要翻译: 公开了具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽(OFLDT)部分的半导体器件结构。 体积半导体层(BSL)设置有厚度BSLT> TCD。 一个大的沟槽顶部区域(LTTA)映射到BSL顶部,其几何形状等于OFLDT。 LTTA被划分为散置的,互补的临时区域ITA-A和ITA-B。 通过去除对应于ITA-B的散装半导体材料,在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。 对应于ITA-A的剩余体积半导体材料被转化为氧化物。 如果在经过转换的ITA-A之间仍然留有剩余空间,则剩余空间被氧化物沉积填满。 重要的是,所有ITA-A和ITA-B的几何形状都应该被简单而小型化,以便于快速有效地进行氧化物转换和氧化物填充。