公开(公告)号：US5872982A

公开(公告)日：1999-02-16

申请号：US688555

申请日：1996-07-30

Applicant: Roger E. Tipley

Inventor： Roger E. Tipley

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: In general, in one aspect, the invention features a method for reducing the elapsed period between the time an interrupt acknowledge is issued by a CPU and the time when the corresponding interrupt vector is received at the CPU. When a device connected to a lower speed bus sends an interrupt request, an interrupt queue device, connected to the CPU by a higher speed bus, intercepts the interrupt request, temporarily stores the corresponding interrupt vector and then responds to an interrupt acknowledge from the CPU by delivering the temporarily stored interrupt vector on the higher speed bus. In addition, the interrupt queue can deliver the temporarily stored interrupt vector to the CPU on a separate serial line.

Abstract translation: 通常，一方面，本发明的特征在于一种用于减少在CPU发出中断确认的时间与在CPU处接收相应中断向量的时间之间经过的时间段的方法。 当连接到较低速总线的设备发送中断请求时，通过较高速总线连接到CPU的中断队列设备将截取中断请求，临时存储相应的中断向量，然后从CPU响应中断确认 通过在较高速总线上传递临时存储的中断向量。 此外，中断队列可以将临时存储的中断向量传递到单独的串行线路上的CPU。

公开(公告)号：US5872939A

公开(公告)日：1999-02-16

申请号：US658485

申请日：1996-06-05

Applicant: Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

Inventor： Jens K. Ramsey ,  Alan L. Goodrum ,  Paul R. Culley

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00

CPC classification number: G06F13/364

Abstract: Access to a bus in a computer system having a CPU and bus devices capable of running cycles on a bus is controlled by an arbiter. The arbiter grants access to the bus according to an arbitration scheme that depends on whether a request for the bus is pending from the CPU, in which a first arbitration scheme arbitrates between the bus devices, and wherein a second arbitration scheme arbitrates between the CPU and at least one other bus device if the CPU request is present.

Abstract translation: 具有能够在总线上运行循环的CPU和总线设备的计算机系统中的总线的访问由仲裁器控制。 仲裁器根据仲裁方案授予对总线的访问，该仲裁方案取决于来自CPU的总线请求是否等待，其中第一仲裁方案在总线设备之间进行仲裁，并且其中第二仲裁方案在CPU和 如果存在CPU请求，则至少另外一个总线设备。

公开(公告)号：US5868480A

公开(公告)日：1999-02-09

申请号：US773793

申请日：1996-12-17

Applicant: Mehdi Zeinali

Inventor： Mehdi Zeinali

IPC: G02B5/20 ,  G02B26/08 ,  G02F1/13357 ,  H04N9/31 ,  G03B21/14

CPC classification number: G02F1/133621 ,  G02B26/0841 ,  G02B5/201 ,  H04N9/3108

Abstract: A projection apparatus provides a projection engine that supplies polarized light to a dielectric filter (or diffraction grating). The dielectric filter provides an array of pixels that each pass selected colors of light and reflect other colors. Each pixel is subpixelated (for example, red, green, and blue subpixels) so that a single subpixel passes a selected color (for example, red) and reflects the other colors (for example, green and blue). A digital micromirror device has an array of mirrors that correspond in number to the number of subpixels of the dielectric filter. Each of the mirrors provide "on" and "off" positions for selectively transmitting a desired color of light from the mirror to an image screen. The image screen receives light reflected by selected of the mirrors of the array of micromirrors when the selected mirrors are in the "on" position. The micromirror device can be controlled with a computer, television, signal, video signal, or the like.

Abstract translation: 投影装置提供将偏振光提供给介质滤光器（或衍射光栅）的投影引擎。 介质滤波器提供像素阵列，每个像素通过所选择的光的颜色并反射其他颜色。 每个像素被子像素化（例如，红色，绿色和蓝色子像素），使得单个子像素通过所选择的颜色（例如，红色）并且反映其他颜色（例如，绿色和蓝色）。 数字微镜器件具有数量相对于介质滤波器的子像素数目的反射镜阵列。 每个反射镜提供“开”和“关”位置，用于选择性地将所需颜色的光从反射镜传输到图像屏幕。 当所选择的反射镜处于“打开”位置时，图像屏幕接收由选定的微镜阵列的反射镜反射的光。 微镜装置可以用计算机，电视，信号，视频信号等进行控制。

公开(公告)号：US5867444A

公开(公告)日：1999-02-02

申请号：US937535

申请日：1997-09-25

Applicant: Hung Q. Le ,  Sompong P. Olarig

Inventor： Hung Q. Le ,  Sompong P. Olarig

IPC: G11C8/00

CPC classification number: G11C7/1045 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C2207/105

Abstract: A programmable memory device including a register that stores a programmable mode select bit, a data input, a control input and decode circuitry that decodes the mode select bit to determine whether the memory device operates in either a check mode or a mask mode. The control input receives at least one control bit for each data byte received by the memory device during a write operation or cycle. The function of the control bit(s) depends upon the mode select bit. In a check mode of operation, each control bit functions as a parity/check bit for a corresponding data byte, where the memory device stores the check bit with its corresponding data byte during each write cycle. In the mask mode of operation, each control bit functions as a mask bit for a corresponding data byte, where the memory device selectively stores or masks the data byte depending upon the state of the corresponding mask bit.

Abstract translation: 一种可编程存储器件，包括存储可编程模式选择位的寄存器，数据输入，解码模式选择位的控制输入和解码电路，以确定存储器件是否以检查模式或掩模模式工作。 在写入操作或周期期间，控制输入接收由存储器件接收的每个数据字节的至少一个控制位。 控制位的功能取决于模式选择位。 在检查操作模式中，每个控制位用作相应数据字节的奇偶校验位，其中存储器件在每个写入周期期间将检查位与其对应的数据字节存储。 在掩模操作模式中，每个控制位用作相应数据字节的掩码位，存储器件根据对应的掩码位的状态有选择地存储或屏蔽数据字节。

公开(公告)号：US5862063A

公开(公告)日：1999-01-19

申请号：US770346

申请日：1996-12-20

Applicant: Gary W. Thome ,  John S. Thayer

Inventor： Gary W. Thome ,  John S. Thayer

IPC: G10H7/00 ,  G06F7/38 ,  G06F17/10

CPC classification number: G10H7/002 ,  G10H2210/305

Abstract: An apparatus and a method for massaging audio signal perform interpolation, dynamic filtering, and panning on the audio signal represented as a matrix of input values. In the interpolation process, the input values are loaded into first and second vector registers, while fractional coefficients are loaded into a third vector register. Next, the first vector register is subtracted from the second vector register. Additionally, in a single operation, the routine performs a vector multiply operation between the second and third registers and accumulates the result of the vector multiply operation in the second register. The results are saved and the process is repeated until all input values in the matrix have been processed. In the dynamic filtering process, after the data loading step, for each slot in said vector register, the routine performs a multiply operation between the filter coefficient and the slot of the vector register and accumulates the result of the multiply operation in the slot of the second register in a single clock cycle while it retains data of the remaining slots in the vector register in the same clock cycle. The results are saved and the process is repeated until all input values in the matrix have been processed. In the stretching process, after loading data in the appropriate vector register, the routine copies the content of each slot of the vector register into consecutive pair of slots on a second vector register and when the second vector register is full, copies the content of each of the remaining slots in the first vector register into consecutive pairs of slots on a third register. In the panning process, the routine performs a vector multiply operation between the first vector register and a coefficient vector register for each slot in the first vector register. This vector multiply operation is preferably a 32-bit vector multiply operation which is broken down into a low order extended precision multiply accumulate operation and a high order extended precision multiply accumulate operation.

公开(公告)号：US5856795A

公开(公告)日：1999-01-05

申请号：US935034

申请日：1997-09-22

Applicant: Kenneth W. Arnold ,  Harold S. Merkel

Inventor： Kenneth W. Arnold ,  Harold S. Merkel

IPC: G06F11/00 ,  G05B14/02

CPC classification number: G06F3/0238 ,  G06F3/023 ,  G06F11/006

Abstract: A keyboard matrix of a keyboard has drive lines including a set of lines to be selectively activated for detection of depressed keys and scan lines including a set of lines to be selectively monitored for detection of depressed keys. The keyboard matrix includes circuitry for connecting one of the drive lines with one of the scan lines for providing an identification of the keyboard.

Abstract translation: 键盘的键盘矩阵具有包括一组线的驱动线，所述一组线被选择性地激活以检测按下的键和扫描线，所述扫描线包括要选择性地监视的一组线以便检测按下的键。 键盘矩阵包括用于将驱动线之一与扫描线之一连接以提供键盘的识别的电路。

公开(公告)号：US5854742A

公开(公告)日：1998-12-29

申请号：US935842

申请日：1997-09-23

Applicant: Richard A. Faulk

Inventor： Richard A. Faulk

IPC: G05F1/565 ,  H02M3/335 ,  G05F1/56

CPC classification number: H02M3/33507 ,  G05F1/565

Abstract: A current-mode control system for a switching power supply which provides logarithmic compensation to a peak primary current of a variable frequency, fully discontinuous switching power supply. A ramp voltage generator generates a ramp voltage that is furnished to a control circuit. The control circuit compares the voltage level of the ramp signal to the voltage level of a control voltage. The control voltage is provided by an error amplifier and is a function of an output voltage of the converter. The control circuit allows a primary switching current to exist in the converter until the ramp voltage renders the control voltage. The ramp voltage logarithmically compensates the peak of the primary current by adjusting the ramp voltage. This logarithmic compensation provides a relatively constant output power over a large input voltage range.

Abstract translation: 一种用于开关电源的电流模式控制系统，其向可变频率，完全不连续的开关电源的峰值初级电流提供对数补偿。 斜坡电压发生器产生提供给控制电路的斜坡电压。 控制电路将斜坡信号的电压电平与控制电压的电压电平进行比较。 控制电压由误差放大器提供，并且是转换器的输出电压的函数。 控制电路允许转换器中存在初级开关电流，直到斜坡电压提供控制电压。 斜坡电压通过调整斜坡电压对数地补偿初级电流的峰值。 该对数补偿在大输入电压范围内提供相对恒定的输出功率。

公开(公告)号：US5850559A

公开(公告)日：1998-12-15

申请号：US693458

申请日：1996-08-07

Applicant: Michael F. Angelo ,  Craig A. Miller

Inventor： Michael F. Angelo ,  Craig A. Miller

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/30 ,  G06F21/00 ,  G06F11/00

CPC classification number: G06F1/26 ,  G06F1/30 ,  G06F21/81

Abstract: A computer system that automatically and securely executes registered programs immediately prior to a transition to a reduced energy consumption state. A registrar table specifying registered programs and a secure modification detection value for each registered program are maintained in system management mode memory or other secure memory space in the computer system. A system management interrupt is generated following a request to remove power from the computer system or the occurrence of an event that triggers an energy saving mode. The system management interrupt handler routine then generates a current modification detection value for each registered program. The current modification detection values are compared with the secure modification detection values. Execution of a registered program is permitted if the values match. After all registered programs have been executed, the computer system automatically powers down or enters an energy saving mode. The computer system thereby allows secure and convenient execution of programs or commands that would typically interfere with normal computer use.

Abstract translation: 一种计算机系统，其在转换到降低的能量消耗状态之前立即自动且安全地执行注册的程序。 在计算机系统中的系统管理模式存储器或其他安全存储器空间中保持指定注册程序的登记器表和每个注册程序的安全修改检测值。 在从计算机系统移除电力的请求或触发节能模式的事件的发生之后，产生系统管理中断。 然后，系统管理中断处理程序例程为每个注册的程序生成当前的修改检测值。 将当前修改检测值与安全修改检测值进行比较。 如果值匹配，则允许执行注册的程序。 所有注册程序执行完毕后，电脑系统会自动关机或进入节能模式。 因此，计算机系统允许安全和方便地执行通常会干扰正常计算机使用的程序或命令。

公开(公告)号：US5850227A

公开(公告)日：1998-12-15

申请号：US771755

申请日：1996-12-20

Applicant: Brian E. Longhenry ,  John S. Thayer

Inventor： Brian E. Longhenry ,  John S. Thayer

IPC: G06T3/40 ,  G06F5/00

CPC classification number: G06T3/4007

Abstract: A routable operand and selectable operation processor multimedia extension unit is employed to stretch pixel bit images in a video system using an efficient, parallel technique. For a series of pixels in a row, a series of interpolation values are established, based on multiples of a reciprocal of a stretch factor. For each interpolation value, the integral portion is used to establish the appropriate two source pixels, and the fractional portion then provides weighting of those pixel values. The various source pixels and interpolation values are routed using the operand routing and operated upon using the vector selectable operations, yielding two destination pixels calculated in parallel.

Abstract translation: 使用可路由操作数和可选择的操作处理器多媒体扩展单元来使用有效的并行技术在视频系统中拉伸像素比特图像。 对于一行中的一系列像素，基于拉伸因子的倒数的倍数建立一系列内插值。 对于每个内插值，积分部分用于建立适当的两个源像素，然后分数部分提供那些像素值的加权。 使用操作数路由路由各种源像素和内插值，并在使用向量可选操作时操作，产生并行计算的两个目标像素。

公开(公告)号：US5841795A

公开(公告)日：1998-11-24

申请号：US599757

申请日：1996-02-12

Applicant: Sompong Paul Olarig ,  William L. Walker

Inventor： Sompong Paul Olarig ,  William L. Walker

IPC: G06F11/10 ,  G11C29/00

CPC classification number: G06F11/1016 ,  G06F11/1028

Abstract: A method of detecting and correcting errors in a memory subsystem of a computer is described. The method includes beginning a write operation of N data bits to a memory, generating M check bits from the N data bits, writing the N data bits and the M check bits to the memory, reading the N data bits and M check bits from the memory, generating X syndrome bits from the N data bits and the M check bits, and using the X syndrome bits to detect and correct errors. Preferably, the M check bits are generated also from A address bits corresponding to the location in memory to which the N data bits and M check bits are to be written.

Abstract translation: 描述了一种检测和校正计算机的存储器子系统中的错误的方法。 该方法包括开始对存储器进行N个数据位的写操作，从N个数据位产生M个校验位，将N个数据位和M个校验位写入存储器，读取N个数据位和M个校验位 存储器，从N个数据位和M个校验位生成X个校正子位，并使用X校验位来检测和校正错误。 优选地，也可以从对应于要写入N个数据位和M个校验位的存储器中的位置的A地址位产生M个校验位。