Abstract:
An electronic amplifier circuit comprising an operational amplifier circuit, such as a two-stage operational amplifier circuit, in tandem with a operational transconductance amplifier. The electronic amplifier circuit has high open-loop gain and high gain-bandwidth while maintaining stability over a wide range of operating parameters.
Abstract:
A precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The invention has a oscillation generator and two independent current generators. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current which is independent of temperature. The precision relaxation oscillator with temperature compensation is implemented on a single, monolithic integrated circuit.
Abstract:
A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller further includes an on-chip temperature sensor, used in conjunction with the A/D converter, to monitor the temperature of the microcontroller. The temperature sensor generates and uses a differential voltage that is obtained across the base-emitter functions of two compatible bipolar transistors having dissimilar emitter areas. This differential voltage is proportional to temperature and may be sampled by the A/D converter to obtain a digital count indicative of the temperature of the microcontroller.
Abstract:
A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.
Abstract:
In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.
Abstract:
A method provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed, each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared to a threshold value. An action related to the thermal protection function is initiated upon the integration output of an affected component exceeding the threshold value.
Abstract:
A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.
Abstract:
A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.
Abstract:
A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.