Load and line regulation using operational transconductance amplifier and operational amplifier in tandem
    91.
    发明授权
    Load and line regulation using operational transconductance amplifier and operational amplifier in tandem 有权
    串联使用工作跨导放大器和运算放大器进行负载和线路调节

    公开(公告)号:US07091785B2

    公开(公告)日:2006-08-15

    申请号:US10857332

    申请日:2004-05-28

    CPC classification number: H03F3/4521

    Abstract: An electronic amplifier circuit comprising an operational amplifier circuit, such as a two-stage operational amplifier circuit, in tandem with a operational transconductance amplifier. The electronic amplifier circuit has high open-loop gain and high gain-bandwidth while maintaining stability over a wide range of operating parameters.

    Abstract translation: 一种电子放大器电路,包括与运算跨导放大器串联的诸如两级运算放大器电路的运算放大器电路。 电子放大器电路具有高开环增益和高增益带宽,同时在宽范围的工作参数下保持稳定性。

    Microcontroller with on-chip linear temperature sensor
    93.
    发明授权
    Microcontroller with on-chip linear temperature sensor 失效
    具有片上线性温度传感器的微控制器

    公开(公告)号:US5619430A

    公开(公告)日:1997-04-08

    申请号:US541666

    申请日:1995-10-10

    Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller further includes an on-chip temperature sensor, used in conjunction with the A/D converter, to monitor the temperature of the microcontroller. The temperature sensor generates and uses a differential voltage that is obtained across the base-emitter functions of two compatible bipolar transistors having dissimilar emitter areas. This differential voltage is proportional to temperature and may be sampled by the A/D converter to obtain a digital count indicative of the temperature of the microcontroller.

    Abstract translation: 公开了一种用于电池充电和监视应用的微控制器。 微控制器包括微处理器和各种前端模拟电路,其包括斜率A / D转换器和多路复用器,用于允许将多个模拟输入信号转换成指示信号电平的相应数字计数。 微控制器还包括与A / D转换器结合使用的片上温度传感器,以监视微控制器的温度。 温度传感器产生并使用在具有不同发射极区域的两个兼容双极晶体管的基极 - 发射极功能之间获得的差分电压。 该差分电压与温度成比例,可以由A / D转换器采样,以获得指示微控制器温度的数字计数。

    Integrated analog-to-digital converter
    94.
    发明授权
    Integrated analog-to-digital converter 失效
    集成模数转换器

    公开(公告)号:US4937577A

    公开(公告)日:1990-06-26

    申请号:US65939

    申请日:1987-06-23

    Abstract: A feedback coder, which employs simple CMOS push/pull amplifiers as gain elements, along with a bistable circuit, in its preferred embodiment takes the form of a second-order delta-sigma modulator. The output of the modulator is converted into pulse code modulated words by a finite impluse response filter which incorporates a partial coefficient generator utilizing simplified logic. The generator output is provided to an accumulator in which the stage operate at reduced speed. A simple multiplexer generates a serial output. The entire converter can be integrated on a semiconductor chip of relatively small area.

    Abstract translation: 在其优选实施例中采用简单CMOS推/拉放大器作为增益元件的反馈编码器连同双稳态电路采用二阶Δ-Σ调制器的形式。 调制器的输出通过有限的模拟响应滤波器转换成脉冲码调制字,该滤波器包含利用简化逻辑的部分系数发生器。 发电机输出被提供给一个蓄能器,在该蓄能器中,该级以较低的速度工作。 一个简单的多路复用器产生串行输出。 整个转换器可集成在相对较小面积的半导体芯片上。

    Processor having Switch Instruction Circuit

    公开(公告)号:US20240394062A1

    公开(公告)日:2024-11-28

    申请号:US18534203

    申请日:2023-12-08

    Abstract: In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.

    IC thermal protection
    97.
    发明授权

    公开(公告)号:US12088285B2

    公开(公告)日:2024-09-10

    申请号:US17548988

    申请日:2021-12-13

    CPC classification number: H03K17/0822 G01K7/01 H02H5/044 H03K2017/0806

    Abstract: A method provides thermal protection for an IC device that has multiple components. For each component, temperatures are sensed, each of which associated with a different area of the respective component and a respective temperature sense signal is output indicative of the highest sensed temperature of the respective component. For each of the components, the respective temperature sense output signal is sampled to produce a sequence of discrete sampled temperature values. A sequence of differences between a reference temperature value and each of the discrete sample temperatures is integrated over time to compute, for each of the components, a respective integration output. The respective integration output computed for each of the switches is compared to a threshold value. An action related to the thermal protection function is initiated upon the integration output of an affected component exceeding the threshold value.

    Machine learning assisted quality of service (QoS) for solid state drives

    公开(公告)号:US11934696B2

    公开(公告)日:2024-03-19

    申请号:US17398091

    申请日:2021-08-10

    CPC classification number: G06F3/0659 G06F3/0611 G06F3/0679 G06N3/08

    Abstract: A method for meeting quality of service (QoS) requirements in a flash controller that includes one or more instruction queues and a neural network engine. A configuration file for a QoS neural network is loaded into the neural network engine. A current command is received at the instruction queue(s). Feature values corresponding to commands in the instruction queue(s) are identified and are loaded into the neural network engine. A neural network operation of the QoS neural network is performed using as input the identified feature values to predict latency of the current command. The predicted latency is compared to a first latency threshold. When the predicted latency exceeds the first latency threshold one or more of the commands in the instruction queue(s) are modified. The commands are not modified when the predicted latency does not exceed the latency threshold. A next command in the instruction queue(s) is then performed.

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