公开(公告)号：US11895829B2

公开(公告)日：2024-02-06

申请号：US17837718

申请日：2022-06-10

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Pei-Rou Jiang ,  Chao-Wen Lay

IPC分类号： H10B12/00

CPC分类号： H10B12/482

摘要： The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.

公开(公告)号：US20240040776A1

公开(公告)日：2024-02-01

申请号：US18485293

申请日：2023-10-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chiang-Lin SHIH ,  Hsueh-Han LU ,  Yu-Ting LIN

IPC分类号： H10B12/00

CPC分类号： H10B12/485 ,  H10B12/09 ,  H10B12/34 ,  H10B12/50

摘要： A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

公开(公告)号：US20240032283A1

公开(公告)日：2024-01-25

申请号：US17870073

申请日：2022-07-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10805

摘要： A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

公开(公告)号：US20240030133A1

公开(公告)日：2024-01-25

申请号：US18197816

申请日：2023-05-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L23/5329 ,  H01L21/76841 ,  H01L21/76885 ,  H01L21/76837

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer positioned on sidewalls of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. The plurality of outer liner layers include one or in more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

公开(公告)号：US20240030132A1

公开(公告)日：2024-01-25

申请号：US17870087

申请日：2022-07-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L23/5329 ,  H01L21/76885 ,  H01L21/76841 ,  H01L21/76837

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of first conductive structures positioned on the substrate; a plurality of outer liner layer positioned on sidewalls of the plurality of first conductive structures; and a plurality of bottom inter-feature dielectric layers positioned on the plurality of outer liner layers and between the plurality of first conductive structures. The plurality of outer liner layers include one or to more species of vanadium oxide. The plurality of bottom inter-feature dielectric layers are porous.

公开(公告)号：US20240027518A1

公开(公告)日：2024-01-25

申请号：US17813934

申请日：2022-07-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Chung WANG

IPC分类号： G01R31/28

CPC分类号： G01R31/2834 ,  G01R31/2831

摘要： The present disclosure provides a wafer testing method, including: assigning multiple testing programs to multiple wafers, wherein each of the testing programs includes testing algorithms configured to measure parameters of the wafers; setting multiple sets of testing conditions for the testing programs; and testing at least one of the wafers by executing a corresponding one of the testing programs according to a corresponding one of the testing conditions.

公开(公告)号：US11881453B2

公开(公告)日：2024-01-23

申请号：US18124757

申请日：2023-03-22

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chia-Hsiang Hsu

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L23/00 ,  H01L27/088 ,  H01L27/12

CPC分类号： H01L23/528 ,  H01L21/7682 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/5329 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/76816 ,  H01L24/33 ,  H01L27/0886 ,  H01L27/1211

摘要： The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.

公开(公告)号：US20240023313A1

公开(公告)日：2024-01-18

申请号：US18218218

申请日：2023-07-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YING-CHIEH LAI

IPC分类号： H10B12/00

CPC分类号： H10B12/34 ,  H10B12/053

摘要： A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

公开(公告)号：US11876063B2

公开(公告)日：2024-01-16

申请号：US17462330

申请日：2021-08-31

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih Shih

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L2224/02372 ,  H01L2224/05093 ,  H01L2224/32012 ,  H01L2224/33104

摘要： A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

公开(公告)号：US11876000B2

公开(公告)日：2024-01-16

申请号：US17550317

申请日：2021-12-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chia-Hsiang Hsu

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31116

摘要： A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming an energy-sensitive layer over the target layer. The method also includes performing a first energy treating process to form a first treated portion in the energy-sensitive layer, and performing a second energy treating process to form a second treated portion in the energy-sensitive layer. The method further includes removing the first treated portion and the second treated portion to form a first opening and a second opening in the energy-sensitive layer, and transferring the first opening and the second opening into the target layer.