公开(公告)号：US20050028004A1

公开(公告)日：2005-02-03

申请号：US10817148

申请日：2004-04-02

Applicant: Andrew Dellow ,  Peter Bennett

Inventor： Andrew Dellow ,  Peter Bennett

IPC: G06F12/14 ,  G06F21/57 ,  G06F21/72 ,  H04L9/00

CPC classification number: G06F21/72 ,  G06F12/1441 ,  G06F21/57 ,  G06F2221/2105

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor. An additional instruction monitor checks the code instructions from the CPU and also impairs the operation of the circuit unless the address of code requested is in a given range. The code is in the form of a linked list and the range is derived as a linked list table during a first check.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证者处理器自动运行，并且不能通过与主处理器相同的内部总线接收应用代码而被欺骗。 附加的指令监视器检查来自CPU的代码指令，并且还损害电路的操作，除非所请求的代码的地址在给定的范围内。 代码是链表的形式，并且在第一次检查期间将该范围派生为链表。

公开(公告)号：US20040105242A1

公开(公告)日：2004-06-03

申请号：US10714760

申请日：2003-11-17

Applicant: STMicroelectronics Limited

Inventor： Paul Evans

IPC: H05K007/10

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

公开(公告)号：US20030196041A1

公开(公告)日：2003-10-16

申请号：US10446280

申请日：2003-05-23

Applicant: STMicroelectronics Limited

Inventor： Andrew Craig Sturges ,  David May

IPC: G06F012/00

CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Abstract translation: 提供一种缓存系统，其包括高速缓冲存储器和高速缓冲存储器补充机制，其根据主存储器中的项目的地址将高速缓冲存储器中的一组高速缓存分区中的一个或多个分配给项目。 这在所描述的实施例之一中通过用项目的地址包括一组分区选择器位来实现，所述分组选择器位允许生成分区掩码以识别可以加载该物品的高速缓存分区。

公开(公告)号：US20030182570A1

公开(公告)日：2003-09-25

申请号：US10354891

申请日：2003-01-30

Applicant: STMicroelectronics Limited

Inventor： Andrew Dellow

IPC: G06F011/30

CPC classification number: G06F21/575 ,  G06F21/64

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证者处理器自动运行，并且不能通过与主处理器相同的内部总线接收应用代码而被欺骗。

公开(公告)号：US20030107825A1

公开(公告)日：2003-06-12

申请号：US10171453

申请日：2002-06-13

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics Limited

Inventor： Pierangelo Magni ,  Francesco Sala ,  Eric Christison ,  Andrea Giovanni Cigada

IPC: G02B007/02

CPC classification number: G02B7/022 ,  G02B7/04 ,  H01L31/0203 ,  H01L31/02325 ,  H04N5/2253 ,  H04N5/2254

Abstract: An image-detecting device including: a body housing a sensor; a first supporting element, rigidly coupled with the body and defining a seat; and an objective including at least one optical unit having an optical axis. The seat forms a guide portion engaging directly and slidably an alignment portion formed by said optical unit to keep the optical axis orthogonal to the sensor.

Abstract translation: 一种图像检测装置，包括：容纳传感器的主体; 第一支撑元件，与主体刚性联接并且限定座椅; 以及包括具有光轴的至少一个光学单元的目标。 所述座部形成与所述光学单元形成的对准部分直接且可滑动地接合以使光轴正交于所述传感器的引导部。

公开(公告)号：US20030106048A1

公开(公告)日：2003-06-05

申请号：US10103655

申请日：2002-03-20

Applicant: STMicroelectronics Limited

Inventor： Sean McGoogan ,  Richard Shann

IPC: G06F009/45 ,  G06F009/44

CPC classification number: G06F9/45512 ,  G06F9/44521

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module including a plurality of relocation instructions having at least one information output relocation with a field indicating information to be output, the method including reading a relocation instruction from one of the object code modules, and when the read relocation instruction is an information output relocation, displaying the information indicated in the field in a human readable form.

Abstract translation: 一种从多个目标代码模块形成可执行程序的方法，每个目标代码模块包括具有至少一个信息输出重定位的多个重定位指令，其中一个字段指示要输出的信息，该方法包括从一个目标代码模块读取重定位指令 的目标代码模块，并且当读取重定位指令是信息输出重定位时，以人类可读形式显示在该领域中指示的信息。

公开(公告)号：US20020176233A1

公开(公告)日：2002-11-28

申请号：US10085121

申请日：2002-02-27

Applicant: STMicroelectronics Limited

Inventor： Paul Evans

IPC: H05K007/00

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract translation: 一种用于处理器系统的可堆叠模块，其包括具有安装到其顶侧的一组顶侧电路部件的支撑板以及顶侧和下侧连接器。 该模块可与其他这样的模块堆叠并且设置有导电轨道，其被布置成在堆叠中的模块之间传送传输流数据和传输流控制信号。 还提供了处理器系统中的这种模块的堆叠。

公开(公告)号：US20020146130A1

公开(公告)日：2002-10-10

申请号：US10099589

申请日：2002-03-13

Applicant: STMicroelectronics Limited

Inventor： Andrew R. Dellow

IPC: H04L009/00

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US6097783A

公开(公告)日：2000-08-01

申请号：US221669

申请日：1998-12-23

Applicant: Trevor Monk

Inventor： Trevor Monk

IPC: H03K23/44 ,  H03K23/54 ,  H03K23/66 ,  H03L7/183 ,  H03K21/00

CPC classification number: H03K23/66 ,  H03K23/44 ,  H03K23/54 ,  H03K23/667 ,  H03L7/183

Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages, where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage has an input node connected to the output node of a preceding transistor stage in the ring, an enable node connected to the clock nodes of the transistor stages, and an output node connected to the input node of a subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node, and a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node, wherein control nodes of a first transistor of each said transistor pair are connected together to provide the input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide the clock node for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

Abstract translation: 分频电路包括以环形连接多个M个晶体管级，其中M为偶数整数。 每个晶体管级包括输入节点，时钟节点和输出节点。 三态逆变器级具有连接到环中先前晶体管级的输出节点的输入节点，连接到晶体管级的时钟节点的使能节点和连接到后续晶体管的输入节点的输出节点 在戒指阶段。 每个晶体管级包括串联连接在第一电压电平和输出节点之间的第一导电类型的第一对晶体管，以及串联连接在第二电压电平和所述输出节点之间的第二导电类型的第二对晶体管 其中，每个所述晶体管对的第一晶体管的控制节点连接在一起以提供所述级的输入节点，并且每个所述晶体管对的第二晶体管的控制节点连接在一起以为所述级提供所述时钟节点，由此 当输入时钟信号施加到晶体管级的时钟节点时，在三态反相器的输出节点处产生输出信号，其中每个周期表示输入时钟信号的M个周期。

公开(公告)号：US6072335A

公开(公告)日：2000-06-06

申请号：US972791

申请日：1997-11-18

Applicant: Peter William Hughes

Inventor： Peter William Hughes

IPC: H04N9/64 ,  G05F3/24 ,  H03K5/151 ,  H03K17/042 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/0185

CPC classification number: G05F3/24 ,  H03K17/04206 ,  H03K17/167 ,  H03K5/151

Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

Abstract translation: 输出电流单元包括具有连接在电压供应线和互补输出之间的第一晶体管的共源共栅电路。 第二和第三晶体管由在输出节点和接地线之间具有并联导电路径的反相器电路控制，并联导电路径具有与控制电路不同的载流能力，以切换电流承载路径中较强的电流。