-
91.发明申请公开(公告)号：US20180122470A1
公开(公告)日：2018-05-03
申请号：US15598962
申请日：2017-05-18
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/79 , G11C2213/82
摘要： A non-volatile memory includes a number of bit lines, a number of source lines, and a number of memory cells of a non-volatile type. Each memory cell is coupled between a respective bit line and a respective source line. One or more discharge lines are coupled to a reference-voltage terminal. A number of controlled switches are coupled between a respective source line and a respective discharge line, which can be selectively driven for connecting the respective source line to the respective discharge line so as to form a conductive path between the respective source line and the reference-voltage terminal.
-
公开(公告)号：US20180122464A1
公开(公告)日：2018-05-03
申请号：US15855671
申请日：2017-12-27
发明人： Jason Brand , Jason Snodgress
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/00 , G11C13/0033 , G11C13/004 , G11C29/50 , G11C2029/5002
摘要： A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.
-
公开(公告)号：US20180120405A1
公开(公告)日：2018-05-03
申请号：US15855939
申请日：2017-12-27
发明人： Zengtao T. Liu
CPC分类号： G01R33/58 , G01R33/1284 , G01R33/24 , G11C5/025 , G11C5/063 , G11C7/1087 , G11C7/1093 , G11C8/14 , G11C13/0004 , G11C13/0026 , G11C13/003 , G11C2213/18 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/14 , H01L45/144
摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.
-
公开(公告)号：US09953261B2
公开(公告)日：2018-04-24
申请号：US14990720
申请日：2016-01-07
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
-
公开(公告)号：US09946969B2
公开(公告)日：2018-04-17
申请号：US14990721
申请日：2016-01-07
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
-
公开(公告)号：US20180086534A1
公开(公告)日：2018-03-29
申请号：US15566419
申请日：2016-04-14
CPC分类号： B65D81/18 , F25D3/08 , F25D2303/082 , F25D2303/0822 , F25D2303/085 , F25D2331/804 , F28D20/026 , G11C13/0004 , Y02E60/145
摘要： This present disclosure provides a vessel assembly for use in temperature sensitive shipping that can maintain a payload temperature across a range of temperatures. Importantly, the vessel assembly of the present disclosure reduces the overall packaging materials used in a shipper box and prevents the “wrong” mixture of PCM-containing vessels from being used.
-
公开(公告)号：US09928904B2
公开(公告)日：2018-03-27
申请号：US15500046
申请日：2014-09-26
发明人： Brent Buchanan , Le Zheng
CPC分类号： G11C13/003 , G11C11/1659 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C2213/74 , G11C2213/79
摘要： An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.
-
公开(公告)号：US09922708B1
公开(公告)日：2018-03-20
申请号：US15404829
申请日：2017-01-12
申请人： SK hynix Inc.
发明人： Yun Seok Hong
CPC分类号： G11C13/0004 , G06F1/263 , G11C5/147 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C17/16 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/141
摘要： A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of Ovonic threshold switch (OTS) units. The second voltage terminal may have a voltage different from that of the first voltage terminal. The OTS devices may be connected between the first voltage terminal and the second voltage terminal. The OTS units may be serially connected with each other.
-
公开(公告)号：US20180075906A1
公开(公告)日：2018-03-15
申请号：US15805109
申请日：2017-11-06
发明人： Shine C. Chung
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C17/16 , G11C17/18 , G11C2213/72 , G11C2213/74
摘要： Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.
-
公开(公告)号：US20180075903A1
公开(公告)日：2018-03-15
申请号：US15443084
申请日：2017-02-27
发明人： Ryu OGIWARA , Daisaburo TAKASHIMA
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0054 , G11C2013/0092 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L45/12
摘要： According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.
-
-
-
-
-
-
-
-
-
搜索结果
7380 条记录 (耗时 0.037 秒)
