公开(公告)号：US20100330882A1

公开(公告)日：2010-12-30

申请号：US12774153

申请日：2010-05-05

申请人： Juergen Schwandner ,  Roland Koppert

发明人： Juergen Schwandner ,  Roland Koppert

IPC分类号： B24B1/00 ,  B24D11/00

CPC分类号： B24B37/22 ,  B24B7/22 ,  B24B7/228 ,  B24B37/0056 ,  B24D3/28 ,  B24D11/00 ,  B24D13/147 ,  C09G1/04 ,  H01L21/02024

摘要： A semiconductor wafer is polished, wherein in a first step, the rear side of the wafer is polished by a polishing pad comprising fixedly bonded abrasives having a grain size of 0.1-1.0 μm, while supplying a polishing agent free of solid materials having a pH of at least 11.8, and, in a second step, the front side of the semiconductor wafer is polished, wherein a polishing agent having a pH of less than 11.8 is supplied. A polishing pad for use in apparatuses for polishing semiconductor wafers, has a layer containing abrasives, a layer composed of a stiff plastic and also a compliant, non-woven layer, wherein the layers are bonded to one another by means of pressure-sensitive adhesive layers.

摘要翻译： 抛光半导体晶片，其中在第一步骤中，通过抛光垫抛光晶片的后侧，抛光垫包括具有0.1-1.0μm的粒度的固定粘合的研磨剂，同时供给不含固体物质的抛光剂，其具有pH 为至少11.8，并且在第二步骤中，抛光半导体晶片的前侧，其中提供pH小于11.8的抛光剂。 用于研磨半导体晶片的设备的抛光垫具有含有研磨剂的层，由刚性塑料构成的层以及顺应性无纺布层，其中通过压敏粘合剂将层彼此粘合 层。

公开(公告)号：US20100323586A1

公开(公告)日：2010-12-23

申请号：US12754846

申请日：2010-04-06

申请人： Georg Pietsch

发明人： Georg Pietsch

IPC分类号： B24B7/10

CPC分类号： C09G1/02 ,  B24B37/044 ,  H01L21/02024

摘要： Semiconductor wafers are polished by a material-removing polishing process A, on both sides of the wafer, using an abrasive-free polishing pad, and a polishing agent which contains abrasive; and a material-removing polishing process B, on at least one side of the wafer, using a polishing pad with a microstructured surface containing no materials which contact the wafer which are harder than the semiconductor material, and a polishing agent is added which has a pH≧ to 10 and contains no substances with abrasive action. Preferred is a method for producing a semiconductor wafer, comprising the following ordered steps: separating a semiconductor single crystal into wafers; simultaneously processing both sides of the wafer by chip-removing processing; polishing the wafer, comprising a polishing process A and a polishing process B; and CMP of one side of the wafer, removing

摘要翻译： 使用无研磨抛光垫的抛光剂和含有研磨剂的抛光剂，通过抛光抛光工艺A在晶片的两侧上抛光半导体晶片。 和抛光抛光工艺B，在晶片的至少一侧使用具有不含与半导体材料相比不接触晶片的材料的微结构化表面的抛光垫，以及抛光剂，其具有 pH≥10，不含有研磨作用的物质。 优选半导体晶片的制造方法，其特征在于，包括以下有序步骤：将半导体单晶分离成晶片; 通过芯片去除处理同时处理晶片的两侧; 抛光晶片，包括抛光工艺A和抛光工艺B; 和CMP晶片的一侧，去除<1μm。

公开(公告)号：US07851381B2

公开(公告)日：2010-12-14

申请号：US11806317

申请日：2007-05-31

申请人： Keiji Ishibashi ,  Takayuki Nishiura ,  Masato Irikura ,  Seiji Nakahata

发明人： Keiji Ishibashi ,  Takayuki Nishiura ,  Masato Irikura ,  Seiji Nakahata

IPC分类号： H01L21/304 ,  B24D3/02 ,  B24B57/00

CPC分类号： H01L21/02024 ,  C09G1/02 ,  C30B29/406 ,  C30B33/00 ,  H01L21/02052 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/1305 ,  Y10S438/959 ,  H01L2924/00014 ,  H01L2924/00

摘要： A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least −850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.

摘要翻译： 用于氮化物晶体的表面处理方法是对氮化物晶体的表面进行化学和机械抛光的表面处理方法。 使用氧化物磨粒。 研磨颗粒具有至少为-850kJ / mol的标准自由能，作为每1摩尔氧分子的转化值，Mohs硬度至少为4。表面处理方法有效地提供了有效地获得氮化物 可用于半导体器件的晶体衬底，其上形成有平滑和高质量表面的氮化物晶体。

公开(公告)号：US20100294983A1

公开(公告)日：2010-11-25

申请号：US12733913

申请日：2008-09-29

申请人： Takayuki Matsushita ,  Masashi Teramoto ,  Haruki Nojo

发明人： Takayuki Matsushita ,  Masashi Teramoto ,  Haruki Nojo

IPC分类号： C09K13/00

CPC分类号： C09G1/02 ,  C09K3/1463 ,  C09K13/02 ,  H01L21/02024

摘要： A polishing composition that can improve polishing property without foaming is provided. A polishing composition includes a pH regulator, a water-soluble polymer compound, and a compound containing an alkylene diamine structure having two nitrogens represented by the following general formula (1), and having at least one block type polyether bonded to the two nitrogens of the alkylene structure, the block type polyether having a bond of an oxyethylene group and an oxypropylene group: where R represents an alkylene group represented by CnH2n, in which n is an integer of 1 or more.

摘要翻译： 提供可以提高抛光性而不发泡的抛光组合物。 抛光组合物包括pH调节剂，水溶性聚合物化合物和含有由以下通式（1）表示的具有两个氮的亚烷基二胺结构的化合物，并且具有至少一个与两个氮结合的嵌段型聚醚 亚烷基结构，具有氧化乙烯基和氧化亚丙基的键的嵌段型聚醚：其中R表示由C n H 2n表示的亚烷基，其中n为1或更大的整数。

公开(公告)号：US07786488B2

公开(公告)日：2010-08-31

申请号：US12394477

申请日：2009-02-27

申请人： Masahiro Nakayama ,  Naoki Matsumoto ,  Koshi Tamamura ,  Masao Ikeda

发明人： Masahiro Nakayama ,  Naoki Matsumoto ,  Koshi Tamamura ,  Masao Ikeda

IPC分类号： H01L31/0312

CPC分类号： H01L21/02008 ,  B24B37/08 ,  H01L21/02024 ,  Y10S438/959

摘要： Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.

摘要翻译： 由氮化物和下衬底材料之间的失配导致的，由外延生长的氮化物膜在气相中的外来下衬衬底产生的氮化物半导体晶片具有很强的内部应力。 通过在气相中在GaAs下衬底上堆叠GaN膜而消除GaAs下衬层而制成的GaN晶片由于内部应力而由于GaN和GaAs之间的晶格常数的失配而向上弯曲。

公开(公告)号：US20100090314A1

公开(公告)日：2010-04-15

申请号：US12449017

申请日：2008-01-29

申请人： Naoto Iizuka ,  Hirotaka Kurimoto ,  Koichi Kosaka ,  Fumiaki Maruyama

发明人： Naoto Iizuka ,  Hirotaka Kurimoto ,  Koichi Kosaka ,  Fumiaki Maruyama

IPC分类号： H01L29/34 ,  H01L21/306

CPC分类号： B24B37/042 ,  H01L21/02024

摘要： The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

摘要翻译： 本发明提供了一种用于在最终研磨步骤中将研磨速度设定为10nm /分以下的最终抛光的硅单晶晶片的最终抛光方法，作为用于研磨硅的多个研磨步骤中的最终步骤 将具有抛光浆料的单晶晶片置于硅单晶晶片和抛光垫之间，以及通过该方法进行最终抛光的硅单晶晶片。 因此，可以提供可以获得具有较少PID（抛光诱导缺陷）的硅单晶晶片和通过该方法进行最终抛光的硅单晶晶片的最终抛光方法。

公开(公告)号：US07695347B2

公开(公告)日：2010-04-13

申请号：US10493494

申请日：2002-10-25

申请人： Hisashi Masumura ,  Kazuya Tomii ,  Shigenao Ito ,  Kenichi Anzai ,  Kenichi Inoue

发明人： Hisashi Masumura ,  Kazuya Tomii ,  Shigenao Ito ,  Kenichi Anzai ,  Kenichi Inoue

IPC分类号： B24B7/19 ,  B24B7/30 ,  B24D11/00 ,  B32B3/06

CPC分类号： H01L21/02024 ,  B24B37/042 ,  B24B37/24 ,  Y10T428/249955

摘要： A method for polishing a wafer effectively preventing a sag in an outer peripheral portion of a wafer and a polishing pad for polishing a wafer preferably used in the method for polishing a wafer are provided. The method for polishing a wafer comprises the step of: mirror-polishing a wafer with a main surface of the wafer being in contact with a polishing pad of non-woven fabric impregnated with resin, wherein a ratio of surface roughness of the polishing pad to compressibility thereof {surface roughness Ra (μm)/compressibility (%)} is 3.8 or more.

摘要翻译： 提供了用于抛光晶片的方法，其有效地防止晶片的外周部分的下垂以及用于抛光晶片的抛光垫的抛光垫。 抛光晶片的方法包括以下步骤：将晶片的主表面与浸渍有树脂的无纺织物的抛光垫接触的晶片进行镜面抛光，其中抛光垫的表面粗糙度与 （表面粗糙度Ra（μm）/压缩率（％））为3.8以上。

公开(公告)号：US20100056027A1

公开(公告)日：2010-03-04

申请号：US12542920

申请日：2009-08-18

申请人： Clemens Zapilko ,  Thomas Jaeschke ,  Makoto Tabata ,  Klaus Roettger

发明人： Clemens Zapilko ,  Thomas Jaeschke ,  Makoto Tabata ,  Klaus Roettger

IPC分类号： B24B1/00 ,  B24B7/17

CPC分类号： B24B37/042 ,  H01L21/02024

摘要： Semiconductor wafers are CMP polished by polishing the rear side of the semiconductor wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is higher at the center than at the edge of the rear side; and polishing the front side of the wafer by means of CMP with a material removal with a profile along the diameter of the wafer wherein material removal is lower in the center of the front side than in an edge region of the front side.

摘要翻译： 半导体晶片通过CMP抛光半导体晶片的后侧，通过沿着晶片直径的轮廓去除材料进行抛光，其中材料去除在中心处比后侧的边缘更高; 并且通过CMP沿着沿着晶片直径的轮廓的材料除去材料抛光晶片的前侧，其中在前侧的中心处的材料去除比在前侧的边缘区域更低。

公开(公告)号：US20100019352A1

公开(公告)日：2010-01-28

申请号：US12511514

申请日：2009-07-29

申请人： Stefan Hölzig ,  Gunnar Leibiger

发明人： Stefan Hölzig ,  Gunnar Leibiger

IPC分类号： H01L29/20

CPC分类号： H01L21/02013 ,  C30B29/403 ,  C30B33/00 ,  G01B11/30 ,  H01L21/02024 ,  H01L21/30625

摘要： A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.

摘要翻译： 制备平滑化的III-N，特别是平滑的III-N底物或III-N模板的方法，其中III表示选自Al，Ga和In的周期性系统的III族的至少一种元素，其使用平滑剂，其包含 立方氮化硼磨料颗粒。 该方法在整个基板或晶片表面上提供具有至少40mm直径的大尺寸III-N基板或III-N模板，其均匀性非常低。 在晶片表面与白光干涉仪的映射中，均方根值的标准偏差为5％或更低，在表面或表面附近区域具有非常好的晶体质量，可测量，例如通过 摇摆曲线映射和/或微拉曼映射。

公开(公告)号：US07621799B2

公开(公告)日：2009-11-24

申请号：US11830310

申请日：2007-07-30

申请人： Takashi Sakairi

发明人： Takashi Sakairi

IPC分类号： B24B1/00

CPC分类号： H01L21/02024 ,  B24B9/065

摘要： Disclosed herein is a polishing method for polishing the end surface of a wafer by using a polishing tape, wherein the end surface of the wafer is polished in the condition where a polishing liquid containing an oxidizing agent is supplied to the end surface of the wafer.

摘要翻译： 本文公开了一种通过使用研磨带对晶片的端面进行研磨的抛光方法，其中在将含有氧化剂的研磨液供给到晶片的端面的状态下，对晶片的端面进行研磨。