公开(公告)号：US20080055007A1

公开(公告)日：2008-03-06

申请号：US11890597

申请日：2007-08-06

Applicant: Thomas Biedka

Inventor： Thomas Biedka

IPC: H03L7/00

CPC classification number: H03L7/093 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0991 ,  H03L2207/06

Abstract: The present invention, generally speaking, provides a VCO linearization technique applicable to advanced loop architectures. In particular, the linearization technique is applicable to a mostly-digital frequency locked loop (FLL), phase locked loop (PLL) or the like using multi-point modulation. In an exemplary embodiment, a correction table is used to form a corrected control variable that affects one modulation point only (e.g., a fast modulation path) of the multi-point modulation circuit. The other modulation point (e.g., a slow modulation path) of the multi-point modulation circuit is controlled in accordance with an error-forming circuit including a loop filter. The use of correction within the fast path enables the VCO to achieve more rapid phase changes than would otherwise be possible, an advantage in high-data-rate communications applications, for example.

Abstract translation: 本发明一般地提供一种适用于高级环路架构的VCO线性化技术。 特别地，线性化技术可应用于使用多点调制的大多数数字锁相环（FLL），锁相环（PLL）等。 在示例性实施例中，校正表用于形成影响多点调制电路的一个调制点（例如，快速调制路径）的校正控制变量。 根据包括环路滤波器的误差形成电路来控制多点调制电路的另一调制点（例如，慢调制路径）。 在快速通路中使用校正使得VCO能够实现比否则可能的更快速的相位变化，例如在高数据速率通信应用中的优点。

公开(公告)号：US20080042753A1

公开(公告)日：2008-02-21

申请号：US11840408

申请日：2007-08-17

Applicant: Thomas Bauernfeind ,  Linus Maurer

Inventor： Thomas Bauernfeind ,  Linus Maurer

IPC: H03L7/099 ,  H03C3/09

CPC classification number: H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03L7/093 ,  H03L7/095 ,  H03L7/0991 ,  H03L7/187 ,  H03L7/1976

Abstract: An arrangement for determining a gradient factor for a digitally controlled oscillator has a data alignment device and an identification device. The data alignment device can be supplied a modulation signal, a phase error signal and an oscillator control word. The data alignment device is configured to output a modulation setting word based on the modulation signal, output a time interval magnitude based on the phase error signal and a reference interval, and output an oscillator modulation word based on the oscillator control word. The identification device is configured to adapt and output the gradient factor based on the modulation setting word, the time interval magnitude and the oscillator modulation word.

Abstract translation: 用于确定数字控制振荡器的梯度因子的装置具有数据对准装置和识别装置。 可以向数据对准装置提供调制信号，相位误差信号和振荡器控制字。 数据对准装置被配置为基于调制信号输出调制设置字，基于相位误差信号和参考间隔输出时间间隔幅度，并且基于振荡器控制字输出振荡器调制字。 识别装置被配置为基于调制设置字，时间间隔幅度和振荡器调制字来适应和输出梯度因子。

公开(公告)号：US20080032649A1

公开(公告)日：2008-02-07

申请号：US11878286

申请日：2007-07-23

Applicant: Toru Matsuura

Inventor： Toru Matsuura

IPC: H04B1/18

CPC classification number: H03C3/0941 ,  H03C3/095 ,  H03C3/0975

Abstract: A bandpass type delta sigma modulation section 15 performs delta sigma modulation on an inputted modulation signal such that quantization noise is reduced in a frequency band which requires low noise. An LPF 16 removes a noise component in a high frequency region from the signal on which the delta sigma modulation has been performed. A frequency modulation circuit 1 reduces noise in the frequency band which requires low noise with the bandpass type delta sigma modulation section 15 and the LPF 16, and reduces noise in the vicinity of a direct current component DC with a feedback comparison section 11 and a loop filter 12.

Abstract translation: 带通型ΔΣ调制部分15对输入的调制信号执行ΔΣ调制，使得量化噪声在需要低噪声的频带中减小。 LPF16从已经执行了ΔΣ调制的信号中去除高频区域中的噪声分量。 频率调制电路1通过带通型ΔΣ调制部分15和LPF 16降低需要低噪声的频带中的噪声，并且通过反馈比较部分11和环路减小直流分量DC附近的噪声 过滤器12。

公开(公告)号：US20080007346A1

公开(公告)日：2008-01-10

申请号：US11471147

申请日：2006-06-20

Applicant: Henrik T. Jensen ,  Brima B. Ibrahim

Inventor： Henrik T. Jensen ,  Brima B. Ibrahim

IPC: H03L7/00

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/093

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract translation: 极性发射机包括用于产生宽带宽的RF信号的两点调制锁相环（PLL）。 PLL包括用于接收可变包络调制信号的相位信号并沿着第一信号路径提供相位信号以产生第一频率调制信号的第一输入端和用于接收相位信号并提供相位信号的第二输入端 用于产生第二频率调制信号的第二信号路径。 PLL还包括具有两个调制点的压控振荡器（VCO），一个用于接收第一频率调制信号，另一个用于接收第二频率调制信号。 VCO由第一频率调制信号和第二频率调制信号的集合控制，以将来自IF的相位信号上变频到RF以产生具有宽带宽的RF信号。

公开(公告)号：US20080003953A1

公开(公告)日：2008-01-03

申请号：US11745611

申请日：2007-05-08

Applicant: Ling-Wei Ke ,  Tai Yuan Yu ,  Hsin-Hung Chen

Inventor： Ling-Wei Ke ,  Tai Yuan Yu ,  Hsin-Hung Chen

IPC: H04B1/40

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095

Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator. The modulation processor generates the processed input modulation signal to adjust the division factor of the frequency dividing unit and compensating for distortion induced by the frequency regenerator.

Abstract translation: 一种锁相环频率合成器，包括锁相环，频率再生器和调制处理器，能够抵抗由频率再生器引起的失真并符合传输规范。 锁相环包括检测器，其基于参考信号和反馈信号之间的相位差产生相位检测信号，环路滤波器，产生第一输出调制信号的电压控制振荡器和基于 经处理的输入调制信号，并将第一输出调制信号的频率除以分频因子以产生反馈信号。 频率再生器产生频率范围不与压控振荡器的输出频率范围重叠的第二输出调制信号。 调制处理器产生经处理的输入调制信号，以调整分频单元的分频因子并补偿由频率再生器引起的失真。

公开(公告)号：US07301405B2

公开(公告)日：2007-11-27

申请号：US11202266

申请日：2005-08-12

Applicant: Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

Inventor： Manabu Kawabe ,  Kazuyuki Hori ,  Satoshi Tanaka ,  Yukinori Akamine ,  Masumi Kasahara ,  Kazuo Watanabe

IPC: H03L7/00

CPC classification number: H03L7/107 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0991 ,  H03L7/1974 ,  H03L7/1976

Abstract: The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

Abstract translation: 本发明提供一种包含能够抑制环路增益变化的环路增益电路的PLL电路。 该PLL电路包括由PLL电路内的压控振荡器驱动的计数器，累加计数器的输出的累加器（ACL），以及将ACL的计数值与设计值进行比较的比较运算电路块 预先存储在寄存器中，并且利用ACL计数值与循环增益成反比的事实来检测PLL电路的环路增益。 基于检测结果，通过用电荷泵电流等校正环路增益来校准环路增益。这允许PLL电路保持不会影响构成PLL的每个元件的特性变化的稳定环路特性。

公开(公告)号：US20070200645A1

公开(公告)日：2007-08-30

申请号：US11790017

申请日：2007-04-23

Applicant: Hisashi Adachi ,  Makoto Sakakura

Inventor： Hisashi Adachi ,  Makoto Sakakura

IPC: H03C3/06 ,  H03C3/09

CPC classification number: H03C3/0966 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03L7/1976 ,  H03M7/3022 ,  H03M7/3037 ,  H03M7/304 ,  H04L27/12

Abstract: A voltage controlled oscillator 1, a variable frequency divider 2, a phase comparator 3, and a loop filter 4 form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part M2 of the frequency division factor data with modulation data X by using an output signal of the variable frequency divider 2 as a clock. An output signal of the sigma-delta modulator 5 is added to an integral part M1 of the frequency division factor data, and the resultant data becomes effective frequency division factor data 13 of the variable frequency divider 2. An output signal of the sigma-delta modulator 5 also becomes control data 14 after passing through a D/A converter 6, a low-pass filter 7, and an amplitude adjustment circuit 8. The control data 14 is inputted into a frequency modulation terminal of the voltage controlled oscillator 1. Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.

Abstract translation: 压控振荡器1，可变分频器2，相位比较器3和环路滤波器4形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器2的输出信号作为时钟将分频因子数据的分数部分M 2与调制数据X相加而获得的数据进行调制。 Σ-Δ调制器5的输出信号被加到分频系数数据的整数部分M 1，结果数据成为可变分频器2的有效分频系数数据13。 Σ-Δ调制器5的输出信号也经过D / A转换器6，低通滤波器7和振幅调整电路8后成为控制数据14。 控制数据14被输入到压控振荡器1的调频终端。因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以在宽频率范围内进行调制 基于数字调制信号。

公开(公告)号：US07236063B2

公开(公告)日：2007-06-26

申请号：US10539426

申请日：2004-07-22

Applicant: Taketoshi Ochi ,  Shunsuke Hirano

Inventor： Taketoshi Ochi ,  Shunsuke Hirano

IPC: H03B5/00

CPC classification number: H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

Abstract: A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

Abstract translation: 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20070109067A1

公开(公告)日：2007-05-17

申请号：US11494345

申请日：2006-07-27

Applicant: Cormac O'Sullivan ,  Colin Lyden ,  Hyman Shanan

Inventor： Cormac O'Sullivan ,  Colin Lyden ,  Hyman Shanan

IPC: H03C3/09

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/1976

Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.

Abstract translation: 一种锁相环RF调制器系统，包括一个锁相环电路，该电路具有响应于输入参考信号和反馈信号的相位检测器电路，响应相位检测器电路提供输出信号的振荡器电路，从相位 检测器电路到振荡器电路，以及从振荡器电路到相位检测器电路的反馈路径。 该系统还包括耦合到反馈路径的第一调制端口，耦合到正向通路的第二调制端口，以及响应于调制数据的增益失配检测电路和参考信号与反馈信号之间的相位误差，用于提供指示器 输出信号，其表示第一调制端口和第二调制端口之间的增益失配。

公开(公告)号：US07157979B2

公开(公告)日：2007-01-02

申请号：US10526197

申请日：2003-08-22

Applicant: Adrian G. Spencer ,  Paul R. Marshall

Inventor： Adrian G. Spencer ,  Paul R. Marshall

IPC: H03L7/00

CPC classification number: H03C3/0991 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/197 ,  H03L7/1976

Abstract: A phase lock loop comprises a variable frequency oscillator (20), a divider (30), a phase comparator (40), a gain control stage (240), and a loop filter (50). The frequency response of the loop is measured by superimposing a modulation at a number of different rates on the error signal generated by the phase comparator, and by measuring for each modulation rate the peak-to-peak variation of the loop control signal controlling the oscillator frequency. If, due to errors in component values, the frequency response deviates from its desired value, the loop gain is adjusted to bring the frequency response close to its desired value.

Abstract translation: 锁相环包括可变频率振荡器（20），分频器（30），相位比较器（40），增益控制级（240）和环路滤波器（50）。 环路的频率响应是通过将由多个不同速率的调制叠加在由相位比较器产生的误差信号上，并通过测量每个调制速率来测量控制振荡器的环路控制信号的峰 - 峰变化 频率。 如果由于组件值的错误，频率响应偏离其所需值，则调整环路增益以使频率响应接近其所需值。