公开(公告)号：US07612698B2

公开(公告)日：2009-11-03

申请号：US12145510

申请日：2008-06-25

Applicant: Hiroki Kimura

Inventor： Hiroki Kimura

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: There is provided a test apparatus for testing a device under test, the test apparatus including: a test signal supplying section that supplies a digital input signal for testing purposes, to the device under test; a reference signal output section that outputs an analogue reference signal in accordance with the digital input signal; a difference obtaining section that outputs an analogue difference signal representing a difference between the analogue reference signal and an analogue output signal outputted by the device under test in accordance with the digital input signal; and a determining section that determines whether the analogue output signal shows a defect or not based on the analogue difference signal.

Abstract translation: 提供了一种用于测试被测设备的测试设备，该测试设备包括：测试信号提供部分，用于将测试用的数字输入信号提供给被测设备; 参考信号输出部分，根据数字输入信号输出模拟参考信号; 差分获取部分，输出表示根据数字输入信号的被测器件输出的模拟参考信号和模拟输出信号之间的差的模拟差分信号; 以及确定部，其基于所述模拟差分信号来确定所述模拟输出信号是否显示缺陷。

公开(公告)号：US07561083B2

公开(公告)日：2009-07-14

申请号：US11933038

申请日：2007-10-31

Applicant: David Anderson ,  Jack Weimer

Inventor： David Anderson ,  Jack Weimer

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Methods and apparatus, including computer program products, to test analog to digital converters, are disclosed. In general, data is received that characterizes a first digital code from a device under test at a first analog voltage of an analog signal generator and a second digital code being a digital code threshold, and a step size is generated for another test of the device by performing a calculation by a processor. The calculation may include multiplying a least significant bit size of the device with a difference of the first and second digital codes to generate a product, and dividing the product by a least significant bit size of the analog signal generator. The first digital code may be calculated from results from multiple subtests in the test, where each of the subtests includes multiple analog to digital conversions by the device at the first analog voltage.

Abstract translation: 公开了用于测试模数转换器的方法和装置，包括计算机程序产品。 通常，接收在模拟信号发生器的第一模拟电压下表征来自被测器件的第一数字代码的数据和作为数字代码阈值的第二数字代码，并且为器件的另一测试生成步长 通过执行处理器的计算。 计算可以包括将设备的最低有效位大小与第一和第二数字码的差值相乘以产生乘积，并且将乘积除以模拟信号发生器的最低有效位大小。 可以根据测试中的多个子测试的结果来计算第一个数字代码，其中每个子测验包括该器件在第一个模拟电压下的多个模数转换。

公开(公告)号：US20090109072A1

公开(公告)日：2009-04-30

申请号：US11933038

申请日：2007-10-31

Applicant: David Anderson ,  Jack Weimer

Inventor： David Anderson ,  Jack Weimer

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: Methods and apparatus, including computer program products, to test analog to digital converters, are disclosed. In general, data is received that characterizes a first digital code from a device under test at a first analog voltage of an analog signal generator and a second digital code being a digital code threshold, and a step size is generated for another test of the device by performing a calculation by a processor. The calculation may include multiplying a least significant bit size of the device with a difference of the first and second digital codes to generate a product, and dividing the product by a least significant bit size of the analog signal generator. The first digital code may be calculated from results from multiple subtests in the test, where each of the subtests includes multiple analog to digital conversions by the device at the first analog voltage.

Abstract translation: 公开了用于测试模数转换器的方法和装置，包括计算机程序产品。 通常，接收在模拟信号发生器的第一模拟电压下表征来自被测器件的第一数字代码的数据和作为数字代码阈值的第二数字代码，并且为器件的另一测试生成步长 通过执行处理器的计算。 计算可以包括将设备的最低有效位大小与第一和第二数字码的差值相乘以产生乘积，并且将乘积除以模拟信号发生器的最低有效位大小。 可以根据测试中的多个子测试的结果来计算第一个数字代码，其中每个子测验包括该器件在第一个模拟电压下的多个模数转换。

公开(公告)号：US20090105992A1

公开(公告)日：2009-04-23

申请号：US11876691

申请日：2007-10-22

Applicant: Michael Frank Jones

Inventor： Michael Frank Jones

IPC: G06F17/40

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.

Abstract translation: 公开了多个存储器的配置和利用，以有效地收集多个设备或单个设备的直方图数据。 每个存储器可以根据要测试的ADC的数量进行配置。 不是为每个ADC使用单独的直方图引擎，或者是重复存储器来测试每个ADC，每个直方图引擎的存储器可以用于具有大的或其他实质的采样宽度的单个ADC，或者可以用于多个ADC，每个具有 较小的样品宽度。 为了实现这一点，使用地址解码将存储器分割成多个段，使得单个ADC可以使用所有段用于直方图数据采集，而多个ADC可以各自使用一个段用于直方图数据采集。

公开(公告)号：US20080158028A1

公开(公告)日：2008-07-03

申请号：US11965752

申请日：2007-12-28

Applicant: Chao-Chi Yang ,  Yao-Ren Fan

Inventor： Chao-Chi Yang ,  Yao-Ren Fan

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/109 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804 ,  H03M1/808

Abstract: The present invention provides a signal converting apparatus with built-in self test, including a first signal converting circuit, a second signal converting circuit, a comparing apparatus, a control logic apparatus and a voltage divider. The first and the second signal converting circuit take a first and a second reference voltage and are respectively controlled by a first and second set of control signals from the control logic apparatus for the comparing apparatus to generate a comparing result.

Abstract translation: 本发明提供一种具有内置自检的信号转换装置，包括第一信号转换电路，第二信号转换电路，比较装置，控制逻辑装置和分压器。 第一和第二信号转换电路采用第一和第二参考电压，并且分别由用于比较装置的控制逻辑装置的第一和第二组控制信号控制以产生比较结果。

公开(公告)号：US07356424B2

公开(公告)日：2008-04-08

申请号：US10672609

申请日：2003-09-26

Applicant: Patrick T. Bohan

Inventor： Patrick T. Bohan

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/00 ,  G06F17/00

CPC classification number: H03M1/109 ,  H03M1/168

Abstract: The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.

Abstract translation: 本发明涉及一种与具有对应于其阶段的代码序列的流水线模数转换器（ADC）一起使用的诊断编译器。 在一个实施例中，诊断编译器包括被配置为确定代码序列的转换位置的转换定位器。 诊断编译器还包括耦合到转换定位器并被配置为基于转换位置提供ADC的至少一个特性的特性指示符。

公开(公告)号：US07095346B2

公开(公告)日：2006-08-22

申请号：US10973656

申请日：2004-10-26

Applicant: Peter Bogner

Inventor： Peter Bogner

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/167 ,  H03M1/44 ,  H03M1/804

Abstract: An A/D converter has at least one converter stage which, respectively, has a sample and hold circuit for sampling an analog input signal. The converter stage also includes a comparator unit that compares the analog input signal with a reference value in order to produce a digital output value from the converter stage, a digital/analog converter for converting the digital output value into an analog signal, a subtractor for subtracting the analog signal from the sampled input signal, a signal amplifier for amplifying the output signal which is output by the subtractor with a particularl singal gain factor for the next converter stage, and a weighting unit for multiplying the digital output value by a multiplier for addition to further weighted output values from converter stages to produce the digital output value from the A/D converter.

Abstract translation: A / D转换器具有至少一个转换器级，其分别具有用于对模拟输入信号进行采样的采样和保持电路。 转换器级还包括比较器单元，其将模拟输入信号与参考值进行比较，以便产生来自转换器级的数字输出值，用于将数字输出值转换为模拟信号的数/模转换器，减法器 从采样输入信号中减去模拟信号，用于放大由减法器输出的输出信号的信号放大器，用于下一个转换器级的特定单位增益因子;以及加权单元，用于将数字输出值乘以乘法器 加上来自转换器级的进一步的加权输出值，以产生来自A / D转换器的数字输出值。

公开(公告)号：US20050116846A1

公开(公告)日：2005-06-02

申请号：US10973656

申请日：2004-10-26

Applicant: Peter Bogner

Inventor： Peter Bogner

IPC: H03M1/10 ,  H03M1/16 ,  H03M1/44 ,  H03M1/80 ,  H03M1/06 ,  H03M1/38

CPC classification number: H03M1/109 ,  H03M1/167 ,  H03M1/44 ,  H03M1/804

Abstract: An A/D converter has at least one converter stage which, respectively, has a sample and hold circuit for sampling an analog input signal. The converter stage also includes a comparator unit that compares the analog input signal with a reference value in order to produce a digital output value from the converter stage, a digital/analog converter for converting the digital output value into an analog signal, a subtractor for subtracting the analog signal from the sampled input signal, a signal amplifier for amplifying the output signal which is output by the subtractor with a particularl singal gain factor for the next converter stage, and a weighting unit for multiplying the digital output value by a multiplier for addition to further weighted output values from converter stages to produce the digital output value from the A/D converter.

Abstract translation: A / D转换器具有至少一个转换器级，其分别具有用于对模拟输入信号进行采样的采样和保持电路。 转换器级还包括比较器单元，其将模拟输入信号与参考值进行比较，以便产生来自转换器级的数字输出值，用于将数字输出值转换为模拟信号的数/模转换器，减法器 从采样输入信号中减去模拟信号，用于放大由减法器输出的输出信号的信号放大器，用于下一个转换器级的特定单位增益因子;以及加权单元，用于将数字输出值乘以乘法器 加上来自转换器级的进一步的加权输出值，以产生来自A / D转换器的数字输出值。

公开(公告)号：US06891486B1

公开(公告)日：2005-05-10

申请号：US10722416

申请日：2003-11-28

Applicant: Visvesvaraya A. Pentakota ,  Jagannathan Venkataraman ,  Vineet Mishra

Inventor： Visvesvaraya A. Pentakota ,  Jagannathan Venkataraman ,  Vineet Mishra

IPC: H03M1/10 ,  H03M1/16 ,  H04L20060101

CPC classification number: H03M1/109 ,  H03M1/168

Abstract: An on-chip calibration circuit which can dynamically (i.e., in operational environment) measure the capacitor mismatch in an ADC using sampling capacitors to sample an input signal and a feedback capacitor (in combination with an amplifier) for amplification. The measured values can be used to generate accurate digital codes representing analog signal samples. The calibration circuit connects the capacitors to various voltage levels and measures the mismatch levels by examining various signals (e.g., the digital codes) generated in such situations.

Abstract translation: 可以动态地（即在操作环境中）的片上校准电路使用采样电容器测量ADC中的电容器失配，以对放大的输入信号和反馈电容器（与放大器组合）进行采样。 测量值可用于产生表示模拟信号样本的精确数字代码。 校准电路将电容器连接到各种电压电平，并通过检查在这种情况下产生的各种信号（例如，数字代码）来测量失配水平。

公开(公告)号：US20050093723A1

公开(公告)日：2005-05-05

申请号：US10912179

申请日：2004-08-06

Applicant: Chun Wei Lin

Inventor： Chun Wei Lin

IPC: H03M1/10

CPC classification number: H03M1/109 ,  H03M1/12

Abstract: A built-in-self-test apparatus for an analog-to-digital converter includes a digital-to-analog converter, a low-pass filter, a histogram analyzer and a software engine. The digital-to-analog converter is intended to generate a first signal. The low-pass filter is intended to smoothen the first signal so that an analog-to-digital converter can perform sampling on the smoothened first signal by a second signal, wherein the bit number of the second signal is greater than or equal to that of the first signal, and the frequency of the second signal is a multiple of that of the first signal. The histogram analyzer is electrically connected to the output end of the analog-to-digital converter. The software engine is electrically connected to the output end of the histogram analyzer so as to display the characteristics of the analog-to-digital converter.

Abstract translation: 用于模数转换器的内置自检装置包括数模转换器，低通滤波器，直方图分析器和软件引擎。 数模转换器旨在产生第一信号。 低通滤波器旨在平滑第一信号，使得模数转换器可以通过第二信号对平滑的第一信号执行采样，其中第二信号的位数大于或等于 第一信号，第二信号的频率是第一信号的倍数。 直方图分析仪电连接到模数转换器的输出端。 软件引擎电连接到直方图分析仪的输出端，以显示模数转换器的特性。