公开(公告)号：US20040199803A1

公开(公告)日：2004-10-07

申请号：US10829938

申请日：2004-04-23

申请人： FUJITSU LIMITED

发明人： Takaaki Suzuki ,  Yukinori Kodama ,  Sumie Kodama

IPC分类号： G06F001/12 ,  G06F001/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/172 ,  Y02D50/20

摘要： A semiconductor integrated circuit is disclosed that operates in synch with a clock signal supplied from an external source, and by a voltage supplied by a power supply. The circuit includes a detection means for detecting that at least one of a frequency of the clock signal and the supply voltage is reduced, and an internal voltage reduction means for lowering an internal voltage of the semiconductor integrated circuit when the detection means detects that at least one of the frequency and the supply voltage is lowered.

摘要翻译： 公开了一种半导体集成电路，其与从外部源提供的时钟信号和由电源提供的电压同步工作。 该电路包括检测装置，用于检测时钟信号和电源电压的频率中的至少一个被降低;以及内部电压降低装置，用于当检测装置检测到至少一个时，降低半导体集成电路的内部电压 频率和电源电压之一降低。

公开(公告)号：US20040163006A1

公开(公告)日：2004-08-19

申请号：US10641706

申请日：2003-08-15

申请人： Marvell Semiconductor Israel Ltd.

发明人： Eitan Rosen

IPC分类号： G06F001/12

CPC分类号： G11C7/1078 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

摘要： A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.

摘要翻译： 采样装置包括第一延迟电路和并联配置的第二延迟电路，其中第一延迟电路和第二延迟电路响应于时钟信号。 数据采样电路可以使用第一延迟电路的输出和第二延迟电路的输出来对与时钟信号同步的数据信号进行采样。 数据信号和时钟信号可以根据双数据速率（DDR）协议进行同步。

公开(公告)号：US20040143775A1

公开(公告)日：2004-07-22

申请号：US10751437

申请日：2004-01-06

发明人： Wen Li ,  Christopher K. Morzano

IPC分类号： G06F001/12

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2254

摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., null1100,null is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

摘要翻译： 公开了一种用于校准数字电路的输入数据路径的校准电路。 在数据路径上发送诸如“1100”的重复数据模式的简单串。 数字电路使用时钟信号捕获数据，检查预定模式的数据信号，并调整施加到数据信号的延迟，直到识别出预定模式。 然后进一步调整延迟直到不再识别预定模式，指示数据的眼睛的边缘接近时钟信号的时钟边缘。 然后对数据信号施加的延迟进一步调整预定量，以将时钟边缘定位在数据眼睛的中心附近。

公开(公告)号：US20040123178A1

公开(公告)日：2004-06-24

申请号：US10324741

申请日：2002-12-18

申请人： International Business Machines Corporation

发明人： Gary Dale Carpenter ,  Vikas Chandra

IPC分类号： G06F013/372 ,  G06F001/04 ,  G06F001/12 ,  G06F005/06

CPC分类号： G06F1/24 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F13/364

摘要： In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when the subsystems are not communicating with one another on the bus. Selected pairs of the subsystems are operated at a shared clock frequency by selectively varying frequencies of clock signals to the subsystems, so that communication can occur at the shared clock frequency on the bus between the selected subsystems, but at different clock frequencies for respective different pairings of the subsystems, and so that the subsystems can operate at independent clock frequencies when not communicating with other ones of the subsystems. Communication among the subsystems is by a bus-based protocol, according to which when a subsystem is granted access to the bus the subsystem has exclusive use of the bus.

摘要翻译： 在一种形式中，用于在集成电路芯片上耦合到计算机系统的总线的子系统之间通信的方法包括当子系统在总线上彼此不通信时以独立的时钟频率操作子系统。 通过选择性地改变到子系统的时钟信号的频率，选择的子系统对以共享时钟频率操作，使得通信可以在所选择的子系统之间的总线上的共享时钟频率处发生，但是对于不同的配对在不同的时钟频率 并且使得子系统可以在不与子系统中的其他子系统通信时以独立的时钟频率工作。 子系统之间的通信是基于总线的协议，根据该协议，当子系统被授权访问总线时，该子系统具有专用的总线。

公开(公告)号：US20040107376A1

公开(公告)日：2004-06-03

申请号：US10605193

申请日：2003-09-14

发明人： William Mar ,  Luke Wen

IPC分类号： G06F001/12

CPC分类号： H03L7/087 ,  H03L7/0991 ,  H04L7/0337

摘要： A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.

摘要翻译： 一种用于提供与输入信号同步的时钟的方法和相关装置。 该方法包括根据输入信号中的转变产生估计速率，处理用于通过将估计速率乘以预定比例来更新估计速率的抖动步骤，以及根据更新的估计速率来调整时钟的频率。 在重复抖动步骤中使用的预定比例根据预定规则进行修改，使得当重复抖动步骤时预定比例不同。

公开(公告)号：US20040088594A1

公开(公告)日：2004-05-06

申请号：US10284245

申请日：2002-10-31

发明人： Karthisha S. Canagasaby ,  Sanjay Dabral ,  Chamath Abhayagunawardhana ,  Ken Drottar ,  David S. Dunning

IPC分类号： G06F001/12

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H04L7/0025

摘要： A receiver circuit is provided with a front amplifier to receive data from an I/O link driven by a remote clock signal; an interpolator to generate a local clock signal to track the remote clock signal encoded in the data; and a tracking mechanism to extract phase information about the remote clock signal from the data and to dynamically adjust the phase of the local clock signal that tracks the remote clock signal in accordance with extracted phase information for subsequent data processing functions, wherein the tracking mechanism is configured to predict the direction of a phase drift, and force the interpolator to move against the phase drift so as to reduce lock time.

摘要翻译： 接收器电路设置有前置放大器，用于从由远程时钟信号驱动的I / O链路接收数据; 内插器，用于产生本地时钟信号以跟踪在数据中编码的远程时钟信号; 以及跟踪机构，用于从数据中提取关于远程时钟信号的相位信息，并且根据用于后续数据处理功能的提取相位信息来动态调整跟踪远程时钟信号的本地时钟信号的相位，其中跟踪机制是 配置为预测相位漂移的方向，并且迫使内插器抵抗相位漂移移动，以便减少锁定时间。

公开(公告)号：US20040083399A1

公开(公告)日：2004-04-29

申请号：US10379403

申请日：2003-03-04

发明人： Martin Vorbach ,  Robert Munch

IPC分类号： G06F001/12

CPC分类号： G06F15/7867

摘要： A method which permits self-synchronization of elements to be synchronized. Synchronization is neither implemented nor managed by a central entity. By shifting synchronization into each element, more synchronization tasks can also be performed simultaneously, because independent elements no longer interfere with one another when accessing the central synchronization entity. In a module with a two- or multi-dimensionally arranged programmable cell structure, each configurable element can access the configuration and status register of other configurable elements over an interconnecting structure and thus can have an active influence on their function and operation. The configuration can thus be accomplished by a load logic from a processing array.

摘要翻译： 允许元件自同步化的方法。 同步既不是由中央实体实现也不是管理的。 通过将同步转移到每个元件中，也可以同时执行更多的同步任务，因为独立元件在访问中央同步实体时不再彼此干扰。 在具有二维或多维布置的可编程单元结构的模块中，每个可配置元件可以通过互连结构访问其他可配置元件的配置和状态寄存器，从而可以对其功能和操作产生积极的影响。 因此，可以通过来自处理阵列的负载逻辑来实现该配置。

公开(公告)号：US20040083398A1

公开(公告)日：2004-04-29

申请号：US10282895

申请日：2002-10-29

申请人： Intel Corporation

发明人： Frank L. Wildgrube ,  Clint J. Hutzenbiler

IPC分类号： G06F001/12

CPC分类号： G06F1/04

摘要： In a multiple-processor platform, various methods are executed for evaluating and harmonizing bus-to-core ratios among the multiple processors. The methods can execute before random-access memory is activated. In one embodiment, the method includes aliasing an advanced programmable interrupt controller base memory specific register to a different address within the system basic input/output system. The methods allow for the addition and/or replacement of processors on the multiple-processor platform. A multiple-processor platform system and a computer-readable medium are also described.

摘要翻译： 在多处理器平台中，执行各种方法来评估和协调多个处理器之间的总线到核心比率。 方法可以在随机存取存储器被激活之前执行。 在一个实施例中，该方法包括将高级可编程中断控制器基本存储器特定寄存器混叠到系统基本输入/输出系统内的不同地址。 这些方法允许在多处理器平台上添加和/或更换处理器。 还描述了多处理器平台系统和计算机可读介质。

公开(公告)号：US20040064749A1

公开(公告)日：2004-04-01

申请号：US10261533

申请日：2002-09-30

发明人： Byron D. Grossnickle ,  Cangsang Zhao

IPC分类号： G06F001/12

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00071 ,  H03K2005/0011

摘要： A method for a fully digitally controlled delay element with wide delay tuning range and small tuning error. The method of one embodiment comprises receiving a set of digital control bits at a delay element. The set of digital control bits is to alter the amount of delay provided from the delay element to an input signal. A driving current through a first driver of the delay element is adjusted with the digital control bits. A capacitance on an output node of the delay element is adjusted with the digital control bits. The output is a delayed version of the input signal based on the driving current and the capacitance.

摘要翻译： 一种具有宽延迟调谐范围和小调谐误差的完全数字控制延迟元件的方法。 一个实施例的方法包括在延迟元件处接收一组数字控制位。 该组数字控制位是将延迟元件提供的延迟量改变为输入信号。 通过数字控制位来调节通过延迟元件的第一驱动器的驱动电流。 延迟元件的输出节点上的电容用数字控制位进行调整。 输出是基于驱动电流和电容的输入信号的延迟版本。

公开(公告)号：US20040049707A1

公开(公告)日：2004-03-11

申请号：US10649523

申请日：2003-08-27

发明人： David Hartwell

IPC分类号： G06F001/12

CPC分类号： G06F1/24

摘要： A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems

摘要翻译： 一种用于初始化和重置在数据处理系统的输入/输出接口内具有定相锁相环（PLL）的时钟子系统的系统和方法。 响应于来自时钟源的时钟信号，第一定时器产生信号。 第二定时器检测来自第一定时器的信号的存在或不存在，并且响应于不存在向电路输出电路复位信号。 电路又向PLL和其他系统发出复位信号