公开(公告)号：US20050006706A1

公开(公告)日：2005-01-13

申请号：US10615171

申请日：2003-07-09

申请人： Evgueniy Stefanov ,  Rene Escoffier

发明人： Evgueniy Stefanov ,  Rene Escoffier

IPC分类号： H01L21/762 ,  H01L27/02 ,  H01L29/74 ,  H01L29/76 ,  H01L21/332

CPC分类号： H01L27/0262 ,  H01L21/76224 ,  H01L29/7436

摘要： In one embodiment, an SCR device (41) includes a p+ wafer (417), a p− layer (416), an n+ buried layer (413) and an n− layer (414). P− wells (411,421) are formed in the n− layer (414). N+ regions (412,422) and p+ regions (415,425) are formed in the p− wells (411,421). A first ohmic contact (431) couples one n+ regions (422) to one p+ region (425). A second ohmic contact (433) couples another n+ region (412) to another p+ region (415) to provide physically and electrically symmetrical low-voltage p-n-p-n silicon controlled rectifiers. A deep isolation trench (419) surrounding the SCR device (41) and dopant concentration profiles provide a low capacitance SCR design for protecting high frequency integrated circuits from electrostatic discharges.

摘要翻译： 在一个实施例中，SCR器件（41）包括p +晶片（417），p-层（416），n +掩埋层（413）和n-层（414）。 P-阱（411,421）形成在n-层（414）中。 在p-阱（411,421）中形成N +区（412,422）和p +区（415,425）。 第一欧姆接触（431）将一个n +区（422）耦合到一个p +区（425）。 第二欧姆接触件（433）将另一个n +区域（412）耦合到另一个p +区域（415），以提供物理和电对称的低压p-n-p-n可控硅整流器。 围绕SCR器件（41）的深隔离沟槽（419）和掺杂剂浓度分布提供了用于保护高频集成电路免受静电放电的低电容SCR设计。

公开(公告)号：US6114193A

公开(公告)日：2000-09-05

申请号：US72584

申请日：1998-05-05

申请人： Yen Hui Chang ,  Kuo Wei Chiang

发明人： Yen Hui Chang ,  Kuo Wei Chiang

IPC分类号： H01L21/329 ,  H01L29/861 ,  H01L21/332

CPC分类号： H01L29/66136 ,  H01L29/861

摘要： A method for preventing the snap down effect in a power rectifier with higher breakdown voltage comprises the step of forming an isolation layer between the semiconductor substrate and the epitaxy layer. The isolation layer can prevent the dislocation occurred upon the semiconductor substrate from influencing the p-n junction atop. Therefore, the power rectifier manufactured by the method of the present invention can work under a higher breakdown voltage exceeding 450 V with reduced cost.

摘要翻译： 一种用于防止具有较高击穿电压的功率整流器中的骤降效应的方法包括在半导体衬底和外延层之间形成隔离层的步骤。 隔离层可以防止在半导体衬底上发生的位错影响顶部的p-n结。 因此，通过本发明的方法制造的功率整流器可以在更高的击穿电压下工作，降低成本。

公开(公告)号：US5981982A

公开(公告)日：1999-11-09

申请号：US847614

申请日：1997-04-28

申请人： John Cuervo Driscoll

发明人： John Cuervo Driscoll

IPC分类号： F02P7/03 ,  F02P15/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/74 ,  H01L21/332 ,  H01L21/335 ,  H01L21/8232

CPC分类号： F02P7/035 ,  F02P15/003 ,  H01L29/0661 ,  H01L29/0839 ,  H01L29/74

摘要： A novel semiconductor switching device is disclosed. The switching device is designed and constructed to include, for example, a highly interdigitated cathode/gate structure on both anode and cathode sides. The semiconductor switching device can be multi-loaded on both anode and cathode sides which provides a great deal of flexibility in operation.

摘要翻译： 公开了一种新颖的半导体开关器件。 开关器件被设计和构造为在阳极和阴极两侧包括例如高度交错的阴极/栅极结构。 半导体开关器件可以在阳极和阴极两侧多重负载，这在操作中提供了极大的灵活性。

公开(公告)号：US5970324A

公开(公告)日：1999-10-19

申请号：US847615

申请日：1997-04-28

申请人： John Cuervo Driscoll

发明人： John Cuervo Driscoll

IPC分类号： F02P7/03 ,  F02P15/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/74 ,  H01L21/332

CPC分类号： F02P7/035 ,  F02P15/003 ,  H01L29/0661 ,  H01L29/0839 ,  H01L29/74 ,  F02P17/12 ,  H01L2224/11

摘要： Methods for making semiconductor switching devices are disclosed. The switching device is designed and constructed to include, for example, a highly interdigitated cathode/gate structure on both sides of the chip. The semiconductor switching device can be four leaded which provides a great deal of flexibility in operation.

摘要翻译： 公开了制造半导体开关器件的方法。 开关器件被设计和构造为在芯片的两侧包括例如高度交错的阴极/栅极结构。 半导体开关器件可以是四引脚，在操作中提供了很大的灵活性。

公开(公告)号：US5956577A

公开(公告)日：1999-09-21

申请号：US140760

申请日：1998-08-26

申请人： Yoshio Terasawa

发明人： Yoshio Terasawa

IPC分类号： H01L21/18 ,  H01L21/329 ,  H01L21/331 ,  H01L21/332 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78

CPC分类号： H01L29/7397 ,  H01L21/187 ,  H01L29/66348 ,  H01L29/66356 ,  H01L29/66371 ,  H01L29/7392 ,  H01L29/744 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/012

摘要： A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to each other. A gate structure is formed in the first main surface of the first substrate. A highly-doped semiconductor layer is formed in the first main surface of the second substrate and has an impurity-concentration which is higher than that of the substrate body of the second substrate. The first main surfaces of the two substrates are joined with each other, by subjecting the two substrates to a heat treatment so that impurities in the highly-doped semiconductor layer of the second substrate are driven into the surface region of the first substrate, and a diffusion layer is thereby formed in the first main surface of the first substrate.

摘要翻译： 一种具有栅极结构的接合型半导体器件的制造方法。 半导体器件包括每个具有基板主体的第一和第二半导体基板以及彼此相对的第一主表面和第二主表面。 栅极结构形成在第一基板的第一主表面中。 在第二基板的第一主表面上形成高掺杂半导体层，其杂质浓度高于第二基板的基板本体的杂质浓度。 通过对两个基板进行热处理，使第二基板的高掺杂半导体层中的杂质被驱动到第一基板的表面区域中，使两个基板的第一主表面相互连接， 从而在第一基板的第一主表面上形成扩散层。

公开(公告)号：US5940689A

公开(公告)日：1999-08-17

申请号：US885921

申请日：1997-06-30

申请人： Christopher L. Rexer ,  Mark L. Rineheimer ,  John M. S. Neilson ,  Thomas E. Grebs

发明人： Christopher L. Rexer ,  Mark L. Rineheimer ,  John M. S. Neilson ,  Thomas E. Grebs

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/332 ,  H01L21/00

CPC分类号： H01L29/7813

摘要： A method of fabricating a UMOS semiconductor device includes a blanket implant of an N type dopant into a surface of a substrate (for forming source regions), a high energy implant of a P type dopant into the substrate (for forming body regions), an etch through a hard mask to form trenches and mesas (each of the mesas having a source region at its top and a body region below), and concurrently (i) providing a gate dielectric on the sidewalls of the trenches and (ii) redistributing the dopants so that the body regions extend deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches. Contact windows are etched in the mesas to allow electrical contact with the source regions and the body regions. The initial implant of P type dopant may be a blanket implant or an implant through a mask which concentrates the P type dopant in the centers of the mesas.

摘要翻译： 一种制造UMOS半导体器件的方法包括将N型掺杂剂覆盖到衬底的表面（用于形成源极区）中，将P型掺杂剂的高能量注入到衬底（用于形成体区）中， 通过硬掩模蚀刻以形成沟槽和台面（每个台面在其顶部具有源区域和下面的主体区域），并且同时（i）在沟槽的侧壁上提供栅极电介质，以及（ii）重新分配 掺杂剂，使得身体区域在台面的中心下方比邻近沟槽的壁更深地延伸到基底之下。 接触窗被蚀刻在台面中以允许与源区域和身体区域的电接触。 P型掺杂剂的初始注入可以是覆盖注入或通过掩模的注入，其将P型掺杂剂集中在台面的中心。

公开(公告)号：US5879967A

公开(公告)日：1999-03-09

申请号：US788372

申请日：1997-01-27

申请人： Tae-Hoon Kim

发明人： Tae-Hoon Kim

IPC分类号： H01L29/744 ,  H01L21/331 ,  H01L29/10 ,  H01L29/74 ,  H01L29/87 ,  H01L21/332

CPC分类号： H01L29/66333 ,  H01L29/1095

摘要： Methods of forming power semiconductor devices include the steps of forming a relatively highly doped latch-up inhibiting region to suppress the likelihood of parasitic thyristor latch-up in a power semiconductor device such as an insulated-gate bipolar transistor (IGBT). In particular, an insulated-gate bipolar transistor is formed by patterning an insulated gate electrode on a surface of a drift region and then implanting first dopants of second conductivity type (e.g., P-type) at a first depth into the drift region, using the gate electrode as an implant mask. The implanted first dopants are then diffused using a thermal treatment to form a base region (e.g., P- well region). Second dopants of second conductivity type are then implanted into the base region at a second depth, less than the first depth, using the insulated gate electrode as a mask. Third dopants of first conductivity type (e.g., N-type) are also implanted into the base region at a third depth, less than the second depth, using the insulated gate electrode as an implant mask. These opposite conductivity type dopants are then simultaneously diffused laterally and vertically in the base region to define a relatively wide and highly doped latch-up inhibiting region (e.g., P-type) and at least one source region disposed between the latch-up inhibiting region and the surface of the drift region. By implanting the second and third dopants using the same implant mask and then diffusing these dopants simultaneously and for the same duration, a latch-up inhibiting region can be formed as wide in the base region as the at least one source region, when the regions are viewed in transverse cross-section. This inhibits the likelihood that the P-N junction at the edge of the at least one source region will become forward biased during high forward current conduction.

摘要翻译： 形成功率半导体器件的方法包括以下步骤：形成相对高掺杂的闭锁抑制区域，以抑制诸如绝缘栅双极晶体管（IGBT）的功率半导体器件中的寄生晶闸管闩锁的可能性。 特别地，通过对漂移区域的表面上的绝缘栅电极进行图案化，然后在第一深度将第二导电类型（例如，P型）的第一掺杂物注入到漂移区域中，形成绝缘栅双极晶体管，使用 栅电极作为植入物掩模。 然后使用热处理使植入的第一掺杂剂扩散以形成碱基区域（例如，P-阱区域）。 然后使用绝缘栅电极作为掩模，将第二导电类型的第二掺杂剂以比第一深度小的第二深度注入到基极区域中。 使用绝缘栅电极作为植入掩模，第一导电类型（例如，N型）的第三掺杂剂也被注入到第三深度小于第二深度的基极区域中。 然后，这些相反的导电型掺杂剂同时在基极区域中横向和垂直地扩散，以限定相对宽且高度掺杂的闩锁禁止区域（例如，P型）和至少一个源极区域，位于闩锁禁止区域 和漂移区域的表面。 通过使用相同的注入掩模注入第二和第三掺杂剂，然后同时扩散这些掺杂剂并且持续相同的时间，可以在基极区域形成闩锁禁止区域作为至少一个源极区域，当区域 以横截面看。 这抑制了在高正向电流传导期间在至少一个源极区域的边缘处的P-N结将变为正向偏置的可能性。

公开(公告)号：US5738942A

公开(公告)日：1998-04-14

申请号：US580926

申请日：1995-12-29

申请人： Atsuko Kubota ,  Masakatu Kojima ,  Norihiko Tsuchiya ,  Shuichi Samata ,  Masanori Numano ,  Yoshihiro Ueno

发明人： Atsuko Kubota ,  Masakatu Kojima ,  Norihiko Tsuchiya ,  Shuichi Samata ,  Masanori Numano ,  Yoshihiro Ueno

IPC分类号： H01L21/304 ,  C30B15/00 ,  C30B33/00 ,  H01L21/322 ,  H01L21/332 ,  B32B9/00 ,  H01L21/306 ,  H01L23/58 ,  H01L29/04

CPC分类号： C30B29/06 ,  C30B15/00 ,  C30B33/00 ,  H01L21/3221 ,  H01L21/3225 ,  H01L29/66393 ,  Y10S148/06 ,  Y10S148/061

摘要： Provided is a process for producing a semiconductor silicon wafer by which an intrinsic gettering effect can be improved and at the same time the top side can be made free from faults. A silicon ingot is produced and sliced to obtain silicon wafers. Then, a polycrystal silicon depositing film is formed on one side of a silicon wafer, which is subjected to a heat treatment in an inert gas, a reducing gas or a mixture thereof to discharge oxygen from the vicinity of the other side. Alternatively, after discharging oxygen from the silicon wafer by a heat treatment, a polycrystal silicon depositing film may be formed on one side of the silicon wafer.

摘要翻译： 本发明提供一种半导体硅晶片的制造方法，其特征在于能够提高固有的吸杂效果，同时能够使上侧无缺陷。 生产硅锭并切片以获得硅晶片。 然后，在硅晶片的一侧上形成多晶硅沉积膜，该硅晶片在惰性气体，还原气体或其混合物中进行热处理，以从另一侧附近排出氧气。 或者，在通过热处理从硅晶片中排出氧之后，可以在硅晶片的一侧上形成多晶硅沉积膜。

公开(公告)号：US5471074A

公开(公告)日：1995-11-28

申请号：US32680

申请日：1993-03-17

申请人： Robert Pezzani

发明人： Robert Pezzani

IPC分类号： H01L21/332 ,  H01L29/08 ,  H01L29/74 ,  H01L29/747 ,  H01L29/87 ,  H03K17/725

CPC分类号： H01L29/87 ,  H01L29/0834 ,  H01L29/7416

摘要： An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

摘要翻译： 一个 开关包括跨越第一和第二主端子的第一晶闸管，其与第一二极管并联设置，但与第二二极管相反，并且与第二二极管并联设置，但与第二二极管相反方向设置的第二晶闸管。 第一晶闸管具有连接到其栅极区的栅极端子。 第二晶闸管和第二二极管在相同的衬底中垂直实现，它们的导通区域紧密地交错，从而在第二二极管的导通周期之后的极性反转导致第二晶闸管导通。

公开(公告)号：US5460981A

公开(公告)日：1995-10-24

申请号：US319520

申请日：1994-10-07

申请人： Tomohide Terashima ,  Gourab Majumdar

发明人： Tomohide Terashima ,  Gourab Majumdar

IPC分类号： H01L29/78 ,  H01L21/332 ,  H01L21/336 ,  H01L29/06 ,  H01L29/74 ,  H01L29/749

CPC分类号： H01L29/66378 ,  H01L29/0649 ,  H01L29/7455 ,  H01L29/749

摘要： A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3a and 3b, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al--Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a , p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

摘要翻译： 本发明的一般目的是使最大可控电流大，而不会对其它特性产生不利影响。 在p +衬底1上形成的n层2的表面中，由n +扩散区域4a，4b和氧化膜9隔开形成p扩散区域3a，3b和3c。在p扩散区域3a和3b上方， 电极5a和5b通过氧化膜6与周围形成绝缘.Al-Si电极7与p扩散区域3a和n +扩散区域4a接触，而金属电极8与p +衬底1接触 通过插入氧化膜9，防止由n +扩散区域4a，p扩散区域3a，n-层2和p +衬底1组成的晶闸管被致动。