公开(公告)号：US20080089459A1

公开(公告)日：2008-04-17

申请号：US11999162

申请日：2007-12-04

申请人： Peter Vlasenko ,  Dieter Haerle

发明人： Peter Vlasenko ,  Dieter Haerle

IPC分类号： H03D3/24

CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

摘要翻译： 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

公开(公告)号：US07346009B2

公开(公告)日：2008-03-18

申请号：US10262643

申请日：2002-09-30

申请人： David A. Brown ,  Peter B. Gillingham

发明人： David A. Brown ,  Peter B. Gillingham

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/7457

摘要： A lookup table for searching for a longest prefix match for a key is disclosed. The lookup table provides a match for a key in a single search cycle. The number of matches stored in the lookup table is maximized by storing each match in only one location in the lookup table. The binary tree is divided into a plurality of levels and each level has a plurality of subtrees. A subtree descriptor stored for a subtree includes a field for each node in the subtree. The state of the field indicates whether an entry for the node is stored in the table. The bit vector allows indexing of the single match stored for the key.

摘要翻译： 公开了用于搜索密钥的最长前缀匹配的查找表。 查找表提供了单个搜索周期中的键的匹配。 通过将每个匹配存储在查找表中的一个位置来最大化存储在查找表中的匹配数。 二叉树被分成多个级别，每个级别具有多个子树。 为子树存储的子树描述符包含子树中每个节点的字段。 该字段的状态指示节点的条目是否存储在表中。 位向量允许为密钥存储的单个匹配索引。

公开(公告)号：US07194574B2

公开(公告)日：2007-03-20

申请号：US11291673

申请日：2005-11-30

申请人： Lawrence King

发明人： Lawrence King

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： H04L45/00 ,  G11C15/00 ,  H04L45/7453

摘要： A plurality of entities are stored in a single addressable location in a Content Addressable Memory (CAM). A column in a CAM entry is selected for storing an entity based on the property of the entity to distribute the entities among the columns to maximize memory utilization. A match for a search key stored in one of the plurality of columns can be found in a single search operation.

摘要翻译： 多个实体存储在内容可寻址存储器（CAM）中的单个可寻址位置中。 选择CAM条目中的列以基于实体的属性存储实体以在列之间分布实体以最大化内存利用率。 可以在单个搜索操作中找到存储在多个列之一中的搜索关键字的匹配。

公开(公告)号：US07095666B2

公开(公告)日：2006-08-22

申请号：US10691111

申请日：2003-10-22

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/02

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

公开(公告)号：US20060170471A1

公开(公告)日：2006-08-03

申请号：US11050644

申请日：2005-02-03

申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

公开(公告)号：US20050265506A1

公开(公告)日：2005-12-01

申请号：US11195257

申请日：2005-08-01

申请人： Richard Foss ,  Peter Gillingham ,  Graham Allan

发明人： Richard Foss ,  Peter Gillingham ,  Graham Allan

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03D3/24 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

摘要： A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.

摘要翻译： 包括用于同步存储器的时钟施加电路或用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置，以及用于接收时钟输入信号并用于传送时钟的抽头延迟线 驱动信号与时钟输入信号同步但延迟到同步存储器，延迟是时钟周期或时钟输入信号的一小部分。

公开(公告)号：US06880064B1

公开(公告)日：2005-04-12

申请号：US09886650

申请日：2001-06-21

申请人： David A. Brown

发明人： David A. Brown

IPC分类号： G06F12/10 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L45/00 ,  H04L45/7457

摘要： A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.

摘要翻译： 查找单元矩阵组合多个查找单元以提供比查找单元的映射关键字长的搜索关键字的最长前缀匹配。 在发布给查找单元矩阵的单个搜索请求中，将搜索关键字的一部分提供给多个查找单元中的每一个。 查找单元矩阵中的每个查找单元基于作为映射器键转发的搜索关键字的部分和在先前查找单元中的多级搜索的结果来执行结果值的多级搜索。 该搜索产生与存储在一个查找单元中的单个位置的搜索关键字对应的值。

公开(公告)号：US20050068839A1

公开(公告)日：2005-03-31

申请号：US10912768

申请日：2004-08-05

申请人： Robert McKenzie ,  Dieter Haerle ,  Sean Lord

发明人： Robert McKenzie ,  Dieter Haerle ,  Sean Lord

IPC分类号： G11C15/00

CPC分类号： G11C15/043 ,  G11C15/00 ,  G11C15/04

摘要： A Content Addressable Memory array includes a plurality of coupled sub-blocks arranged in rows and columns. Search data received by a first sub-block in a first column of the CAM is propagated to each sub-block in the row to the last sub-block in the last column of the CAM. The search result for the CAM is selected based on the propagated search results for each row of sub-blocks and output on a side of the array opposite from the side receiving the search data.

摘要翻译： 内容可寻址存储器阵列包括以行和列排列的多个耦合子块。 由CAM的第一列中的第一子块接收的搜索数据被传播到该CAM的最后一列中的行中的每个子块到最后一个子块。 基于每行子块的传播搜索结果选择CAM的搜索结果，并且在与接收搜索数据的一侧相反的阵列的一侧上输出。

公开(公告)号：US20040164769A1

公开(公告)日：2004-08-26

申请号：US10730002

申请日：2003-12-09

申请人： Mosaid Technologies, Inc

发明人： Raymond Jit-Hung Sung ,  Duncan George Elliott

IPC分类号： H03K019/096

CPC分类号： H03K19/0963

摘要： A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

摘要翻译： 提供了一种用于单轨多米诺骨牌逻辑电路的系统方法，其中反相和非单调逻辑功能可以集成到几乎零开销的流水线系统中。 这种称为时钟逻辑（CL）-domino的逻辑系列功能完整，同时容忍偏差并最小化必须分配的时钟相位数。 在高偏移（1-FO4）条件下，1GHz下的CL-domino ALU的仿真结果显示，在双轨偏斜容忍多米诺骨牌逻辑中实现的相同ALU的功率降低了41％。 尽管在某些情况下还需要额外的设计工作，但是这种功率降低不会对双轨技术造成性能损失。

公开(公告)号：US20040136226A1

公开(公告)日：2004-07-15

申请号：US10691111

申请日：2003-10-22

申请人： MOSAID Technologies Inc.

发明人： Richard C. Foss

IPC分类号： G11C011/24

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

摘要翻译： 具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 读出放大器各自连接到对应的数据总线对，辅助数据总线，次级数据总线通过第二存取晶体管连接到数据总线读出放大器，以及用于使能第二存取晶体管的装置，由此每个主数据总线对可以被多个 阵列的相应行中的读出放大器和辅助数据总线可以由多个pri共享 玛丽数据总线对。