公开(公告)号：US20080227245A1

公开(公告)日：2008-09-18

申请号：US12112104

申请日：2008-04-30

申请人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

发明人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。

公开(公告)号：US20080149930A1

公开(公告)日：2008-06-26

申请号：US11961149

申请日：2007-12-20

申请人： Je-Hun LEE ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

发明人： Je-Hun LEE ,  Chang-Oh Jeong ,  Eun-Guk Lee ,  Do-Hyun Kim

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/4908

摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper, copper solid solution layer.

摘要翻译： 提供线结构，制造线的方法，薄膜晶体管（TFT）基板和制造TFT基板的方法。 导线结构包括形成在基板上并包括铜，铜固溶体层的阻挡层。

公开(公告)号：US20080128689A1

公开(公告)日：2008-06-05

申请号：US11947725

申请日：2007-11-29

申请人： Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

发明人： Je-hun Lee ,  Dong-ju Yang ,  Tae-hyung Ihn ,  Do-hyun Kim ,  Sun-young Hong ,  Seung-jae Jung ,  Chang-oh Jeong ,  Eun-guk Lee

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/7869

摘要： Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

摘要翻译： 提供一种制造半导体氧化物薄膜晶体管（TFT）衬底的方法。 该方法包括在绝缘基板上形成栅极布线; 并且形成其中半导体氧化物膜图案和数据布线堆叠在栅极布线上的结构，其中半导体氧化物膜图案被选择性地图案化以具有第二厚度的第一厚度的沟道区域和源极/漏极区域，并且其中图像数据 通过形成在源极区域上的数据布线耦合到源极区域。 根据4掩模实施例，数据布线和半导体氧化膜图案由共享蚀刻掩模限定。

公开(公告)号：US20080079006A1

公开(公告)日：2008-04-03

申请号：US11850922

申请日：2007-09-06

申请人： Hong-Sick PARK ,  Bong-Kyun KIM ,  Chang-Oh JEONG ,  Jong-Hyun CHOUNG ,  Sun-Young HONG ,  Won-Suk SHIN ,  Byeong-Jin LEE

发明人： Hong-Sick PARK ,  Bong-Kyun KIM ,  Chang-Oh JEONG ,  Jong-Hyun CHOUNG ,  Sun-Young HONG ,  Won-Suk SHIN ,  Byeong-Jin LEE

IPC分类号： H01L29/04 ,  C09K13/08 ,  H01L21/00 ,  H01L23/52

CPC分类号： C09K13/08 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2320/0223 ,  H01L23/53238 ,  H01L27/124 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

摘要翻译： 薄膜面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，包括源电极的数据线和形成的漏电极 在所述栅极绝缘层或所述半导体层上形成的像素电极和与所述漏极连接的像素电极，其中所述栅极线和所述数据线和漏极的至少一个包括由钼Mo-Nb铌合金构成的第一导电层，以及 由含铜铜金属制成的第二导电层。

公开(公告)号：US20080073674A1

公开(公告)日：2008-03-27

申请号：US11944130

申请日：2007-11-21

申请人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

发明人： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC分类号： H01L29/49

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

摘要： The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

摘要翻译： 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US07276732B2

公开(公告)日：2007-10-02

申请号：US11234470

申请日：2005-09-23

申请人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

摘要翻译： 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。

公开(公告)号：US07172913B2

公开(公告)日：2007-02-06

申请号：US11082967

申请日：2005-03-18

申请人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

发明人： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20060205125A1

公开(公告)日：2006-09-14

申请号：US11371057

申请日：2006-03-08

申请人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

发明人： Yang-Ho Bae ,  Chang-Oh Jeong ,  Min-Seok Oh ,  Je-Hun Lee ,  Beom-Seok Cho

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A TFT substrate includes a base substrate, a gate wiring formed on the base substrate, a gate insulation layer, an activation layer, an oxidation-blocking layer, a data wiring, a protection layer and a pixel electrode. The gate wiring includes a gate line and a gate electrode. The gate insulation layer is formed on the base substrate to cover the gate wiring. The activation layer is formed on the gate insulation layer. The oxidation-blocking layer is formed on the activation layer. The data wiring includes a data line, a source electrode and a drain electrode. The source and drain electrodes are disposed on the oxidation-blocking layer therefore lowering the on-current (“Ion”) for turning on the TFT and increasing the off-current (“Ioff”) for turning off the TFT due to the oxidation-blocking layer.

摘要翻译： TFT基板包括基底基板，形成在基底基板上的栅极布线，栅极绝缘层，激活层，氧化阻挡层，数据布线，保护层和像素电极。 栅极布线包括栅极线和栅电极。 栅极绝缘层形成在基底基板上以覆盖栅极布线。 活化层形成在栅绝缘层上。 氧化阻挡层形成在活化层上。 数据线包括数据线，源电极和漏电极。 源电极和漏电极设置在氧化阻挡层上，因此降低导通电流（“I”上“），以便导通TFT并增加截止电流（”I“ “），用于关闭由于氧化阻挡层而导致的TFT。

公开(公告)号：US20060145255A1

公开(公告)日：2006-07-06

申请号：US10548562

申请日：2004-02-28

申请人： Chang-Oh Jeong ,  Beom-Seok Cho ,  Hee-Hwan Choe

发明人： Chang-Oh Jeong ,  Beom-Seok Cho ,  Hee-Hwan Choe

IPC分类号： H01L21/84

CPC分类号： H01L29/78669 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/12 ,  H01L27/124 ,  H01L29/456 ,  H01L29/4908

摘要： Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating layer pattern including silicon and a metal material is coated on the nickel-coated layer. After that, a heat treatment is performed at about 200 to about 350° C. to obtain the nickel-silicide layer. Since the thin film transistor substrate of the LCD device is manufactured by applying the nickel-silicide wiring, a device having low resistivity and good ohmic contact property can be obtained.

公开(公告)号：US20060113670A1

公开(公告)日：2006-06-01

申请号：US11221492

申请日：2005-09-07

申请人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

发明人： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

IPC分类号： H01L23/52

CPC分类号： H01L27/12 ,  H01L21/76838 ,  H01L23/5283 ,  H01L23/53209 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A multi-layer wiring for use with thin film transistors (TFTs), methods of manufacturing the multi-layer wiring, and TFTs employing the multi-layer wiring are provided. In one embodiment, the multi-layer wiring includes a main wiring and a sub-wiring on the main wiring. The main wiring includes a first metal and the sub-wiring includes an alloy wherein a majority of the alloy is the first metal. The multi-layer wiring can exhibit decreased electrical resistance and a reduced tendency to develop malfunctions such as hillocks or spiking. The multi-layer wiring can also exhibit improved contact characteristics with other conductive elements of TFT display devices.

摘要翻译： 提供了用于薄膜晶体管（TFT）的多层布线，多层布线的制造方法以及采用多层布线的TFT。 在一个实施例中，多层布线包括主布线和主布线上的副布线。 主配线包括第一金属，并且子布线包括其中大部分合金是第一金属的合金。 多层布线可以表现出降低的电阻和降低发展故障的倾向，如小丘或尖峰。 多层布线也可以表现出与TFT显示装置的其它导电元件的接触特性的改善。